Fin shape influence on the analog performance of standard and strained MuGFETs

Buhler, R. T.; Martino, João Antônio; Agopian, Paula Ghedini Der; Giacomini, Renato; Simoen, Eddy; Claeys, Cor

doi:10.1109/soi.2010.5641387

Cited by 12 publications

(11 citation statements)

References 1 publication

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“…The most important design parameters for the FinFETs are the shape of Si-fin, doping level in the transistor body and the strain amount in the channel region. These parameters affect carrier mobility and carrier profile as well as the threshold voltage of transistors [9].…”

Section: Resultsmentioning

confidence: 99%

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Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10 20 cm −3 . The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO 2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

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Section: Resultsmentioning

confidence: 99%

“…In FinFETs, the shape, dimensions (height and width) and doping level of the original Si fin have importance in carrier transport [2,[8][9]. The shape of fin plays the role how stress from SiGe is exerted from sidewalls to the central part of body.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Radamson

Luo

Qin

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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“…In FinFETs, Si-fins are processed at initial stage where SiGe is grown to elevate the source/drain regions. In general, a FinFET is designed by parameters such as fins width and height, doping level and geometry of sidewalls (triangular, trapezoid and round shapes) [6]. The trapezoid shape contains a (001) plane at central part and (111) planes at the edges.…”

Section: Transition To Three-dimensional Transistor Designmentioning

confidence: 99%

“…The trap-chip loses its influence on the openings positioned far away from it. 6 Modeling of the SEG of SiGe for recessed openings Figure 19 shows the growth rate and Ge content for SiGe layers grown selectively with different recess depths. These data demonstrate that the growth rate is affected by the recess depth, where deeper openings acquire moderately lower growth rates.…”

Section: Chip Interactions In a Patterned Substratementioning

confidence: 99%

“…In 2003, Intel introduced 90 nm technology node and at that time, nano-electronics received its fundaments [1]. This technological outbreak did not last more than 10 years when 22 nm node was manufactured and the transistor was changed from planar to three-dimensional structure [6][7][8]. The technology roadmap will continue according to ITRS but the ultimate goal for transistor dimensions is not well determined but may be predicted to 5 nm.…”

Section: Introductionmentioning

confidence: 99%

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Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Radamson

Kolahdouz

2015

J Mater Sci: Mater Electron

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Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO

Srishti¹,

Kaur²

2019

Communications in Computer and Information Science

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In this paper, device performance of 14 nm FinFETs have analyzed and electrical parameters like Ion, Ioff, Ion/Ioff, SS, DIBL and power dissipation are measured. These devices have also been analyzed in terms of V-I characteristics. Further, the effect of fin width on device performance was investigated by designing similar FinFETs with different top fin width at 14 nm technology. The designed structures have been simulated using drift diffusion model. In order to validate the results, same structures are also designed & simulated with 20 nm gate length. Also, the FinFETs' performance was optimized using ANN with the PSO algorithm. Both results i.e. optimization results and simulation results were closely matched with 0.48% error.

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Fin shape influence on the analog performance of standard and strained MuGFETs

Cited by 12 publications

References 1 publication

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO

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