Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Radamson, Henry H.; Kolahdouz, Mohammadreza

doi:10.1007/s10854-015-3123-z

Cited by 35 publications

(24 citation statements)

References 66 publications

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“…The SEG of SiGe on Si-Fin and nanowires has its own complexity and challenges. The SiGe growth may suffer from a series of problems: facet formation [54,55], defects, micro-loading, non-uniform strain distribution, surface roughness, and the pattern dependency effect [56,57,58,59,60]. Among those problems, the pattern dependency effect occurs when the density and size of the transistor vary in a chip.…”

Section: Sige Epitaxy Of Nano-scaled Transistorsmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Section: Sige Epitaxy Of Nano-scaled Transistorsmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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“…These sources are usually diluted in H 2 . For Sn growth, SnD 4 and SnCl 4 are the most practical and common sources [23]. Methylsilane (SiH 3 CH 3 ) is widely used for carbon doping in Si and SiGe layers.…”

Section: Chemical Vapor Deposition (Cvd) Techniquementioning

confidence: 99%

Selective Epitaxy of Group IV Materials for CMOS Application

Wang¹,

Radamson²,

Kolahdouz³

2018

Complementary Metal Oxide Semiconductor

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As the International Technology Roadmap for Semiconductors (ITRS) demands an increase of transistor density in the chip, the size of transistors has been continuously shrunk. In this evolution of transistor structure, different strain engineering methods were introduced to induce strain in the channel region. One of the most effective methods is applying embedded SiGe as stressor material in source and drain (S/D) regions by using selective epitaxy. This chapter presents an overview of implementation, modeling, and pattern dependency of selective epitaxy for S/D application in CMOS. The focus is also on the wafer in and ex situ cleaning prior to epitaxy, integrity of gate, and selectivity mode.

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“…The growth of a high-quality Ge layer on Si is one of the main challenges in achieving a vertical GAA structure. So far, many studies have proposed Si/SiGe multilayer structures to create an SiGe channel layer [ 17 , 18 , 19 , 20 , 21 ]. In these studies, the solutions of TMAH, mixture solution HF:H 2 O 2 :CH 3 COOH and other alkaline solutions have often been used to obtain a SiGe channel [ 22 , 23 , 24 , 25 ].…”

Section: Introductionmentioning

confidence: 99%

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

et al. 2020

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With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

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Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

Cited by 35 publications

References 66 publications

Miniaturization of CMOS

Miniaturization of CMOS

Selective Epitaxy of Group IV Materials for CMOS Application

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

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