A Metal-to-Metal (M2M) antifuse is formed using hydrogenated amorphous silicon as a dielectric material between two refractory metal electrodes. The M2M antifuse is used as a programmable device in an FPGA, where it is placed between two interconnect metal layers of a Logic CMOS process. The M2M device may then be programmed to interconnect logic circuits. The resulting programmed link is an alloy of amorphous silicon and barrier metal that forms a low resistance path between the logic circuits.
Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET . The difference between LET at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.
OverviewFunctionality and flexibility has been significantly enhanced with this novel sea of modules FPGA architecture. It includes a new improved logic cell, high performance interconnect architecture and full featured fracturable Flip Flops. The architccture is designed for high in system performance as well as low cost user programmable implementations. A flexible high performance I/O architecture complements the architecture with high performance input / output delays. A modular architecture and design methodology allows quick proliferation to multiple families while tailoring the individual family characteristics to quickly serve a particular market segment. The family uses a novel Metal to Metal antifuse technology that affords high performance, scalability and cost reduction. Architecture GoalsDensity: 5k -200k gates High in-system and I/O performance Modular Architecture and design methodology to provide modular, flexible architecture building blocks allowing multi-family proliferation into marketplace with minimal additional investment. Architecture tailored to High Level Design methodologies. Architecture optimized for a novel Metal to Metal antifuse. Cost efficient family. Support mixed 3/5V in system operation on an individual pin basis Modular ArchitectureA modular architecture and development methodology was adopted to allow rapid multi-family proliferation into the marketplace, with minimal additional investment, to quickly serve individual market segments. Modular, flexible, extensible architecture components were developed to support this requirement. This approach also allowed the fine tuning of the architecture of a targeted family offering to the required specifications without sacrificing efficiency. For example the number of flip flops needed in a product offering can be freely chosen instead of having a fixed number set by the architecture limits, rows and columns. An additional benefit of modular methodology is the exploitation of technology and process advances with minimal additional investment. Modularity supports architectural and design component reusc. Examples of modular architecture components include 1. Register intensive, Logic intensive families are implemcnted by simply varying the C-mod / flip flop ratio . This feature was used to tunc the family architecturc. Different cell clusters [Logic rich or Register rich] arc simply "dropped in" as needed in the same footprint]. VO intensive family VS cost effective family with moderate # I/Os. 2. High density FPGA ScalabilityNovel Fracturable Logic Cell. This module is the culmination of a selection effort from a much larger suite of cells varying in granularity from a simple gate to coarse granularity, including 2-4 input LUT cells. A11 logic cells were benchmarked for logic efficiency, circuit performance and physical layout efficiency. The chosen logic cell is shown in Figure 1. It is an enhanced version of the multiplexer based cell efficiently used in Antifuse FPGAs [l]. The cell is capable of mapping over 4000 useful logic funct...
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