We report a coaxial fiber supercapacitor, which consists of carbon microfiber bundles coated with multiwalled carbon nanotubes as a core electrode and carbon nanofiber paper as an outer electrode. The ratio of electrode volumes was determined by a half-cell test of each electrode. The capacitance reached 6.3 mF cm(-1) (86.8 mF cm(-2)) at a core electrode diameter of 230 μm and the measured energy density was 0.7 μWh cm(-1) (9.8 μWh cm(-2)) at a power density of 13.7 μW cm(-1) (189.4 μW cm(-2)), which were much higher than the previous reports. The change in the cyclic voltammetry characteristics was negligible at 180° bending, with excellent cycling performance. The high capacitance, high energy density, and power density of the coaxial fiber supercapacitor are attributed to not only high effective surface area due to its coaxial structure and bundle of the core electrode, but also all-carbon materials electrodes which have high conductivity. Our coaxial fiber supercapacitor can promote the development of textile electronics in near future.

Seamless stitching of graphene domains on polished copper (111) is proved clearly not only at atomic scale by scanning tunnelling microscopy (STM) and transmission electron micoscopy (TEM), but also at the macroscale by optical microscopy after UV-treatment. Using this concept of seamless stitching, synthesis of 6 cm × 3 cm monocrystalline graphene without grain boundaries on polished copper (111) foil is possible, which is only limited by the chamber size.

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10(-13) A. The resulting devices exhibited an excellent on/off ratio of ~10(5), a high mobility of ~40 cm(2) V(-1) s(-1) and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Semiconducting transition metal dichalcogenides (TMDs) are promising materials for photodetection over a wide range of visible wavelengths. Photodetection is generally realized via a phototransistor, photoconductor, p-n junction photovoltaic device, and thermoelectric device. The photodetectivity, which is a primary parameter in photodetector design, is often limited by either low photoresponsivity or a high dark current in TMDs materials. Here, we demonstrated a highly sensitive photodetector with a MoS/h-BN/graphene heterostructure, by inserting a h-BN insulating layer between graphene electrode and MoS photoabsorber, the dark-carriers were highly suppressed by the large electron barrier (2.7 eV) at the graphene/h-BN junction while the photocarriers were effectively tunneled through small hole barrier (1.2 eV) at the MoS/h-BN junction. With both high photocurrent/dark current ratio (>10) and high photoresponsivity (180 AW), ultrahigh photodetectivity of 2.6 × 10 Jones was obtained at 7 nm thick h-BN, about 100-1000 times higher than that of previously reported MoS-based devices.

Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

cells, [11] and memory. [12,13] Recently, vdWs heterostructure-based nonvolatile optical memory have been investigated for broad potential applications in imaging sensors, [14] logic gates, [15] optoelectronic demodulators, [16] and synaptic devices for neuromorphic systems. [17,18] These 2D vdWs materials and their hybrids are considered to be an ideal platform for nonvolatile optical memory owing to their strong light-matter interactions [19][20][21] and significant photogenerated charge trapping derived from their very large surface-to-volume ratio. [22][23][24] In addition, the mechanical strength and atomic thickness of 2D vdWs materials allow for device miniaturization in flexible and wearable optoelectronics. [25][26][27] The demonstration of 2D vdWs materials-based optical memory in the FETs of few-layer copper indium selenide (CuIn 7 Se 11 ) has been reported [14] along with hybrids of graphene/MoS 2[5] on a silicon substrate. These devices exhibit low optical switching on/off ratios (<1 [5] and ≈10 [14] ), high off-currents (≈400 µA [5] and 20 pA [14] ), and short retention times (50 s [14] ), preventing their use in high quality image sensors and multilevel storage devices.Using oxygen plasma treatments to create more charge trap sites at SiO 2 surface, monolayer MoS 2 -FET-based optical memory on silicon substrate has exhibited a long retention time of ≈10 4 s. [28] However, the data storage capacity of eight levels of the material remains limited for practical applications due to moderate switching on/off ratio of ≈4700. Importantly, the memory function of these devices relies on charge trapping of photoexcited carriers in defects and impurities on either the surface or material/SiO 2 interface. [5,28] This results in short retention times and sensitivity to environmental factors. A charge trapping layer acting as a floating gate, instead of charge trapping at the materials/SiO 2 interface, can be introduced via gold nanoparticle/crosslinked poly(4-vinylphenol)/MoS 2 heterojunction-FETs, which significantly increase both the switching on/off ratio (≈10 6 ) and retention time (>10 4 s). [29] Similarly, by storing charge in the hexagonal boron nitride (h-BN) dielectric layer, the WSe 2 /h-BN-FET-based optical memory on silicon also exhibited a high on/off ratio of 1.1 × 10 6 , realizing a data storage capability of up to 128 distinct states. [30] Despite the long retention time and high on/off ratios of the recently developed vdWs heterostructure-based optical memory 2D van der Waals (vdWs) heterostructures exhibit intriguing optoelectronic properties in photodetectors, solar cells, and light-emitting diodes. In addition, these materials have the potential to be further extended to optical memories with promising broadband applications for image sensing, logic gates, and synaptic devices for neuromorphic computing. In particular, high programming voltage, high off-power consumption, and circuital complexity in integration are primary concerns in the development of three-terminal optical memory devices....

Memristors such as phase-change memory and resistive memory have been proposed to emulate the synaptic activities in neuromorphic systems. However, the low reliability of these types of memories is their biggest challenge for commercialization. Here, a highly reliable memristor array using floating-gate memory operated by two terminals (source and drain) using van der Waals layered materials is demonstrated. Centimeter-scale samples (1.5 cm × 1.5 cm) of MoS as a channel and graphene as a trap layer grown by chemical vapor deposition (CVD) are used for array fabrication with Al O as the tunneling barrier. With regard to the memory characteristics, 93% of the devices exhibit an on/off ratio of over 10 with an average ratio of 10 . The high on/off ratio and reliable endurance in the devices allow stable 6-level memory applications. The devices also exhibit excellent memory durability over 8000 cycles with a negligible shift in the threshold voltage and on-current, which is a significant improvement over other types of memristors. In addition, the devices can be strained up to 1% by fabricating on a flexible substrate. This demonstration opens a practical route for next-generation electronics with CVD-grown van der Waals layered materials.

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2  ×  109 cm−2 eV−1, a thousand times smaller than previously reported values.