Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS ₂ field-effect transistors

Abstract

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2 × 109 cm−2 eV−1, a thousand times smaller than previously reported values.

High‐Performance Monolayer MoS2 Films at the Wafer Scale by Two‐Step Growth

“…An inset in Figure c presents hysteresis amount which is derived from the difference between V THf and V THr . The change in SS may be explained by the effect of the sulfurization temperature on the native defect trap states of ML MoS 2 films, the MoS 2 /HfO 2 interface trap states, or both. Apparently, films that were converted at 900 °C exhibited the smallest trap density.…”

“…Besides the intrinsic quality of the 2D MoS 2 film, the device structure has been known to influence 2D channel transistor performance . Thus, we modified the device structures to study the potential of our two‐step‐grown ML MoS 2 film for various TFT device configurations.…”

Insulators for 2D nanoelectronics: the gap to bridge

“…Slow border traps are typically situated in the insulator within a few nanometers from the interface. They lead to various instabilities of the device threshold voltage, such as flicker (1/f) noise 51,52 , hysteresis 53,54 , and longterm drifts known from Si technologies as bias-temperature instabilities (BTI) 55 .…”

“…4b we compare D it values from literature 14 , 0.9 nm EOT CaF 2 46 , 1.3 nm EOT PTCDA/HfO 2 40 and exfoliated devices of the latter technology 40 . b Comparison of D it values measured for Si devices 78 and different 2D technologies 38,40,41,43,46,54,[73][74][75][76][77] . c Comparison of SS values for different 2D devices 16,38,40,41,43,46,54,66 with EOT below 10 nm.…”

Humidity‐Dependent Characteristics of Few‐Layer MoS2 Field Effect Transistors

“…Hysteresis, dominated by charging/discharging of oxide traps and affected by the defects on the channel, is typically observed in MoS 2 FETs. [39,40] Experimental findings suggest that the absorption of moisture on the oxide or channel surface will greatly affect the hysteresis of MoS 2 FETs exposed to the ambience. [25,41] Figure 5a presents the double sweep transfer curves of the tri-layer MoS 2 FET device.…”