Abstract. With semiconductor technology gradually approaching its physical and thermal limits, recent supercomputers have adopted major
architectural changes to continue increasing the performance through more
power-efficient heterogeneous many-core systems. Examples include Sunway
TaihuLight that has four management processing elements (MPEs) and 256
computing processing elements (CPEs) inside one processor and Summit that has
two central processing units (CPUs) and six graphics processing units (GPUs)
inside one node. Meanwhile, current high-resolution Earth system models that
desperately require more computing power generally consist of millions of
lines of legacy code developed for traditional homogeneous multicore
processors and cannot automatically benefit from the advancement of
supercomputer hardware. As a result, refactoring and optimizing the legacy
models for new architectures become key challenges along the road of taking
advantage of greener and faster supercomputers, providing better support for
the global climate research community and contributing to the long-lasting
societal task of addressing long-term climate change. This article reports
the efforts of a large group in the International Laboratory for
High-Resolution Earth System Prediction (iHESP) that was established by the
cooperation of Qingdao Pilot National Laboratory for Marine Science and
Technology (QNLM), Texas A&M University (TAMU), and the National Center for
Atmospheric Research (NCAR), with the goal of enabling highly efficient
simulations of the high-resolution (25 km atmosphere and 10 km ocean)
Community Earth System Model (CESM-HR) on Sunway TaihuLight. The refactoring
and optimizing efforts have improved the simulation speed of CESM-HR from 1 SYPD (simulation years per day) to 3.4 SYPD (with output disabled) and
supported several hundred years of pre-industrial control simulations. With
further strategies on deeper refactoring and optimizing for remaining
computing hotspots, as well as redesigning architecture-oriented
algorithms, we expect an equivalent or even better efficiency to be gained on the
new platform than traditional homogeneous CPU platforms. The refactoring and
optimizing processes detailed in this paper on the Sunway system should have
implications for similar efforts on other heterogeneous many-core systems
such as GPU-based high-performance computing (HPC) systems.
193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique [1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.
A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks.A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.
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