Mandrel-based patterning: density multiplication techniques for 15nm nodes

Bencher, Chris; Dai, Huixiong; Miao, Liyan; Chen, Yongmei; Xu, Ping; Chen, Yijian; Oemardani, Shiany; Sweis, Jason; Wiaux, Vincent; Hermans, Jan; Chang, Li-Wen; Bao, Xinyu; Yi, He; Wong, H.-S. Philip

doi:10.1117/12.881679

Cited by 19 publications

(13 citation statements)

References 3 publications

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“…SEM images taken from various process steps are also shown in the figure. Compared with the 21-nm line/space data (patterned by an old SATP process [3,5]), 30% improvement in mandrel LWR has been achieved. LWR of the final spacers is also slightly improved.…”

Section: Satp Process Optimization and Simplificationmentioning

confidence: 89%

“…Although EUVL is not ready yet for high-volume semiconductor manufacturing, this EUV+SADP approach and its process development had been reported [5].…”

Section: Cost Analysis Of Satp Process and Other Scaling Candidatesmentioning

confidence: 98%

“…In addition to the scaling difficulty (e.g., due to small-mandrel etching), there are still some questioning voices about the SATP process complexity. Thus, further optimization of SATP process must be carried out in order to compete with several other scaling candidates such as SAQP (self-aligned quadruple patterning) and EUV+SADP schemes [4,5]. In this paper, we shall present the latest progress made to address these critical issues.…”

Section: Introductionmentioning

confidence: 97%

“…Sub-19nm patterning technology poses tremendous challenges to the semiconductor industry, and it has become apparent that adopting multiple patterning techniques [1][2][3][4][5][6] to fill the technology gap due to EUVL lateness will be inevitable. Depending on the device and layout complexity, both overlay requirement and patterning techniques (e.g., either optical or self-aligned multiple patterning) suitable for different semiconductor segments will vary significantly.…”

Section: Introductionmentioning

confidence: 99%

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Mandrel and spacer engineering based self-aligned triple patterning

2012

Self Cite

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Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.

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Section: Satp Process Optimization and Simplificationmentioning

confidence: 89%

“…Although EUVL is not ready yet for high-volume semiconductor manufacturing, this EUV+SADP approach and its process development had been reported [5].…”

Section: Cost Analysis Of Satp Process and Other Scaling Candidatesmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

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Mandrel and spacer engineering based self-aligned triple patterning

2012

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“…com well. Indeed, construction better accurac From a desig case of a des techniques al [9], Directed Beam Direct can be achiev should be con …”

Section: Griddedmentioning

confidence: 98%

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

Belledent

Smayling

Pradelles

et al. 2012

Alternative Lithographic Technologies IV

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A roadmap extending far beyond the current 22nm CMOS node has been presented several times.[1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure.Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography.With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography.For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4.The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin.The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

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Process optimization and simplification of self-aligned triple patterning

Chen

2012

Microelectronic Engineering

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Mandrel-based patterning: density multiplication techniques for 15nm nodes

Cited by 19 publications

References 3 publications

Mandrel and spacer engineering based self-aligned triple patterning

Mandrel and spacer engineering based self-aligned triple patterning

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

Process optimization and simplification of self-aligned triple patterning

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