Process optimization and simplification of self-aligned triple patterning

Chen, Yijian

doi:10.1016/j.mee.2012.06.011

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…Mandrel/spacer engineering based self-aligned multiple patterning (SAMP [10][11][12][13][14][15][16][17][18][19]) techniques have been applied to fabricate advanced logic/DRAM critical layers. Various SAMP schemes, e.g., double (SADP), triple (SATP), quadruple (SAQP), sextuple (SASP), octuple (SAOP) techniques have been reported.…”

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

“…However, its scalability is limited due to the significantly increased process complexity and mask number when extended to more aggressive density-multiplication scenarios. In general, self-aligned quadruple/octuple patterning (SAQP/SAOP) is more capable of increasing the pattern density of 1-D features; while self-aligned triple/sextuple patterning (SATP/SASP) is beneficial to reducing the process complexity by allowing more CD/design freedom and requiring fewer masks [10][11][12][13][14][15][16][17][18][19]. Table 1.…”

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

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Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layerdivision realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.

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Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

Section: Characteristics Of Various Self-aligned Patterning Schemesmentioning

confidence: 99%

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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show abstract

“…Unlike the conventional single-material self-aligned multiple patterning (SAMP) processes [15][16][17][18], a line array fabricated by an altSAMP process is made of two different materials (e.g., A and B) which allow a highly selective etching process to remove one material (ideally) without attacking the other. For example, a line array arranged in an alternating order of A-B-A-B… can be fabricated by an alternating-material self-aligned quadruple/octuple patterning (altSAQP/altSAOP) process, while a line array arranged in a quasialternating order of A-B-B-A-B-B… can be fabricated by an alternating-material self-aligned triple/sextuple (altSATP/altSASP) patterning process.…”

Section: The Alternating-materials Self-aligned Multiple Patterning (Amentioning

confidence: 99%

Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errors

Liu

Han

Chen

2016

Microelectronic Engineering

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Random 2-D layout decomposition and synthesis using self-aligned multiple patterning and stitching techniques

Liu

Zhou

Chen

2015

Microelectronic Engineering

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Process optimization and simplification of self-aligned triple patterning

Cited by 6 publications

References 6 publications

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errors

Random 2-D layout decomposition and synthesis using self-aligned multiple patterning and stitching techniques

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