Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm

Abstract

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks.A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

Sub-20 nm design technology co-optimization for standard cell logic

“…The 10T_BiDir cells are 10 tracks tall and have an acceptable active area efficiency of 66.67%, with restricted-2D M1 that is compatible with cost-effective patterning techniques such as self-aligned double patterning [11].…”

“…A structured grating has unequal line widths and equal spaces [16]. While structured 1D gratings are amenable to cost-effective patterning techniques such as self-aligned double patterning (SADP) [11] and directed self-assembly (DSA) [12], they also provide more design freedom than pure gratings (Section II.C.2). Nevertheless, 1D M1-based standard cells proposed earlier, while having favorable manufacturability, have been unsuccessful in meeting design requirements.…”

Constrained pattern assignment for standard cell based triple patterning lithography

“…Plenty of research efforts have been devoted to TPL [4], [11], [18], [19], [22] [3], [13], [15]- [17]. Bei Yu et al showed that the general TPL decomposition problem is NP-hard, and further proposed an ILP based algorithm to compute legal TPL solutions [22].…”

Layout decomposition for triple patterning lithography

“…Besides, it does not involve any stitch minimization. [13] [14] propose a self-aligned triple patterning (SATP) process to extend 193nm immersion lithography to half-pitch 15nm patterning. But the SATP process cannot insert any stitch, which would greatly constrain the possible layout patterns that are decomposable [15].…”