Constrained pattern assignment for standard cell based triple patterning lithography

Abstract

Triple patterning lithography (TPL) has been recognized as one of the most promising candidates for 14/10nm technology node. Apart from obtaining legal TPL decompositions, various concerns have been raised by the designers, among them consistently assigning the same pattern for the same type of standard cells and balancing the usage of the three masks are two most critical ones. In this paper, a hybrid approach (SAT followed by a sliding-window approach) is proposed targeting at these two problems. To assign the same pattern for the same type of standard cell, we pre-color the boundary polygons of each type of cell by solving a small SAT problem. Following that we propose a sliding-window based approach to compute a locally balanced decomposition. Our algorithm guarantees to find a feasible solution if one exists. Experimental results verify that the problem can be solved very efficiently with the proposed algorithm. Superior locally balanced decompositions are achieved compared with the previous approach in [19].

On Refining Row-Based Detailed Placement for Triple Patterning Lithography

“…The experimental results show that our approach is not only effective but also efficient as compared with a state-of-the-art TPL-aware placer. In the future, we will investigate how to extend or modify our approach to handle the presence of a subset of precolored cells and the requirement of assigning the same coloring solution to cell instances of the same type during detailed placement [18], [19]. We will be also interested in looking into how to take layout decomposition into account at placement stages, including global placement, legalization, and detailed placement, to help further improve the quality of placement.…”

“…From the aspect of layout design, existing research results have focused more on TPL layout decomposition [14], [17], [18], [20], [23], [25] and TPL-aware routing [16], [22] while very few works have been reported for TPL-aware placement [19], [24]. Although the TPL layout decomposition problem is NP-hard for general layouts [25], it has been recently shown that for any standard-cell-based row-structure layout, whether a TPL decomposition solution that has no coloring conflict and no stitch insertion exists for the M1 layer can be exactly determined in polynomial time [20].…”

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

“…LELELE type TPL technology [8][9][10][11][12][13][14][15][16][17][18] in which litho-etch process is repeated three times is often discussed in literature. However, it suffers from native conflict and overlay problems.…”

“…Triple patterning lithography (TPL) is one of the most promising techniques in the 14 nm logic node and beyond. In order to realize a target pattern, various types of techniques including design for manufacturability, such as LELE type double patterning lithograph [1][2][3][4][5][6][7], LELELE type TPL [8][9][10][11][12][13][14][15][16][17][18], LELECUT type TPL [19], and side wall process [20], are used in addition to a basic litho-etch process with optimized mask. These techniques are summarized in [21,22].…”

Layout Decomposition for Triple Patterning Lithography

“…Ghaida et al [17] reused the double patterning techniques. For row-based layout design, Tian et al [19], [21] presented polynomial time decomposition algorithms.…”