Layout Decomposition for Triple Patterning Lithography

Abstract

As minimum feature size and pitch spacing further scale down, triple patterning lithography is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm technology node. Layout decomposition, which divides input layout into several masks to minimize the conflict and stitch numbers, is a crucial design step for double/triple patterning lithography. In this paper, we present a systematic study on triple patterning layout decomposition problem, which is shown to be NP-hard. Because of the NP-hardness, the runtime required to exactly solve it increases dramatically with the problem size. We first propose a set of graph division techniques to reduce the problem size. Then, we develop integer linear programming (ILP) to solve it. For large layouts, even with the graph-division techniques, ILP may still suffer from serious runtime overhead. To achieve better trade-off between runtime and performance, we present a novel semidefinite programming (SDP)-based algorithm. Followed by a mapping process, we can translate the SDP solutions into the final decomposition solutions. Experimental results show that the graph division can reduce runtime dramatically. In addition, SDP-based algorithm can achieve great speedup even compared with accelerated ILP, with very comparable results in terms of the stitch number and the conflict number.Index Terms-Graph division, integer linear programming (ILP), layout decomposition, semidefinite programming (SDP), triple patterning lithography (TPL).

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…The TPL process, however, will be widely used for the 14-nm technology node and beyond [1,6,11]. Thus we conduct TPL statistical variation simulations based on the geometry of the 14-nm technology node [1].…”

“…To resolve BEOL patterning problems, several pitch splitting techniques have been proposed and considered as efficient solutions [2][3][4][5][6][7][8]. Double patterning lithography (DPL), or litho-etch-litho-etch (LELE), has been used for 20-nm logic nodes to pattern interconnect dimensions less than 100 nm [4,9,10].…”

“…Recently, the triple patterning lithography (TPL), or litho-etch-litho-etch-litho-etch (LELELE), has been proposed for backend patterning of a 14-nm node in which the minimum metal pitch can be below 50 nm [1,5,6,11,12]. In TPL, three individual layers or masks can be generated in a layout decomposition as a direct extension of DPT.…”

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…In general, there exist two types of MPL, Litho-Etch-Litho-Etch (LELE) type and self-aligned type. LELE-type of MPL allows stitch insertions and two-dimensional patterns [27], [59], [70], [71], [77], but coloring and overlay compensation schemes become extremely complicated for triple patterning lithography and beyond [12], [15], [30], [38], [60], [73], [76], [81]. Self-aligned type of MPL can minimize electrical variations from overlay and line-edge-roughness but introduces complex coloring and line-end constraints [40], [42], [56].…”

Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errors

“…Nevertheless, the second (line-cut or trench-block) step requires a challenging lithography technique with extremely high resolution and overlay accuracy [8][9]. Therefore, to print the randomly distributed cut holes, we often need to decompose them into three or more masks, which in general leads to an NP-complete coloring problem [10][11]. Another difficult engineering issue is the inevitable edge-placement errors (EPE) mainly due to the overlay errors and CD variations of the cut holes and other involved patterns.…”