Sidewall spacer quadruple patterning for 15nm half-pitch

Abstract

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique [1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

The 2017 Plasma Roadmap: Low temperature plasma science and technology

“…Al 2 O 3 , TiO 2 ) thin films. There is considerable interest currently in growing nitrides such as Si 3 N 4 using PEALD, with one major application being the spacers used during quad-patterning [59]. PEALD, however, has some unique challenges compared to thermal ALD, which would require considerable development to resolve.…”

“…Due to delays in the development of next-generation lithography technologies, such as extreme ultraviolet lithography (EUV), the burden of shrinking microelectronics device dimensions has increasingly fallen on plasma etching and deposition. Techniques, such as quad-patterning [59], require many high-selectivity etch processes and new thin films specially designed for patterning.…”

Self-aligned double patterning (SADP) process even-odd uniformity improvement

“…One is based on the sacrificial core CDU; the other is based on final Sc uniformity post Si etch. [5][6][7] In this paper, we will focus on the space even-odd uniformity propagation from lithography, sacrificial core etch, spacer etch, hard mask etch, and final Si etch. DOMA application will be based on sacrificial core CDU improvement other than final Sc compensation post Si etch, and its final contribution and limitation to the final even-odd uniformity will be clarified by a statistical method.…”

Opportunities and Challenges in Scaling

“…Although pattern pitch on the mask is invariable, the line-and-space ratio is not, and this ratio is directly linked to variation in S 2 and S 4 . It can therefore be seen that CD management is vital in the lithography process [11]. Fig.…”