Advanced beyond-silicon electronic technology requires discoveries of both new channel materials and ultralow-resistance contacts 1,2 . Atomically thin two-dimensional (2D) semiconductors have great potential for realizing high-performance electronic devices 1,3 . However, because of metal-induced gap states (MIGS) 4-7 , energy barriers at the metalsemiconductor interface, which fundamentally lead to high contact resistances and poor current-delivery capabilities, have restrained the advancement of 2D semiconductor transistors to date 2,8,9 . Here, we report a novel ohmic contact technology between semimetallic bismuth and semiconducting monolayer transition metal dichalcogenides (TMDs) where MIGS is sufficiently suppressed and degenerate states in the TMD are spontaneously formed in contact with bismuth. Through this approach, we achieve zero Schottky barrier height, a record-low contact resistance (R C ) of 123 Ω μm, and a recordhigh on-state current density (I ON ) of 1135 µA µm -1 on monolayer MoS 2 . We also demonstrate that excellent ohmic contacts can be formed on various monolayer semiconductors, including MoS 2 , WS 2 , and WSe 2 . Our reported R C values are a significant improvement for 2D semiconductors, and approaching the quantum limit. This technology unveils the full potential of high-performance monolayer transistors that are on par with the state-of-the-art 3D semiconductors, enabling further device down-scaling and extending Moore's Law.The electrical contact resistance at a metal-semiconductor (M-S) interface has been an increasingly critical, yet unsolved issue for the semiconductor industry, hindering the ultimate

The performance and reliability of large-area graphene grown by chemical vapor deposition are often limited by the presence of wrinkles and the transfer-process-induced polymer residue. Here, we report a transfer approach using paraffin as a support layer, whose thermal properties, low chemical reactivity and non-covalent affinity to graphene enable transfer of wrinkle-reduced and clean large-area graphene. The paraffin-transferred graphene has smooth morphology and high electrical reliability with uniform sheet resistance with ~1% deviation over a centimeter-scale area. Electronic devices fabricated on such smooth graphene exhibit electrical performance approaching that of intrinsic graphene with small Dirac points and high carrier mobility (hole mobility = 14,215 cm2 V−1 s−1; electron mobility = 7438 cm2 V−1 s−1), without the need of further annealing treatment. The paraffin-enabled transfer process could open realms for the development of high-performance ubiquitous electronics based on large-area two-dimensional materials.

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The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.ABSTRACT: Lateral heterostructures with planar integrity form the basis of two-dimensional (2D) electronics and optoelectronics. Here we report that, through a twostep chemical vapor deposition (CVD) process, highquality lateral heterostructures can be constructed between metallic and semiconducting transition metal disulfide (TMD) layers. Instead of edge epitaxy, polycrystalline monolayer MoS 2 in such junctions was revealed to nucleate from the vertices of multilayered VS 2 crystals, creating one-dimensional junctions with ultralow contact resistance (0.5 kΩ·μm). This lateral contact contributes to 6-fold improved field-effect mobility for monolayer MoS 2 , compared to the conventional on-top nickel contacts. The all-CVD strategy presented here hence opens up a new avenue for all-2D-based synthetic electronics. See https://pubs.acs.org/sharingguidelines for options on how to legitimately share published articles. Corresponding SEM images. Inset in panel f is the zoomed-in SEM image of a lateral VS 2 −MoS 2 interface (scale bar 2 μm). (g, h) Raman and PL spectra on the central VS 2 region and the surrounding MoS 2 region (blue and red curves, respectively) for the MoS 2 −VS 2 heterostructures. (i) Schematic illustration of MoS 2 growth on presynthesized multilayered VS 2 .

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The large‐area synthesis of high‐quality MoS2 plays an important role in realizing industrial applications of optoelectronics, nanoelectronics, and flexible devices. However, current techniques for chemical vapor deposition (CVD)‐grown MoS2 require a high synthetic temperature and a transfer process, which limits its utilization in device fabrications. Here, the direct synthesis of high‐quality monolayer MoS2 with the domain size up to 120 µm by metal‐organic CVD (MOCVD) at a temperature of 320 °C is reported. Owing to the low‐substrate temperature, the MOCVD‐grown MoS2 exhibits low impurity doping and nearly unstrained properties on the growth substrate, demonstrating enhanced electronic performance with high electron mobility of 68.3 cm2 V−1 s−1 at room temperature. In addition, by tuning the precursor ratio, a better understanding of the MoS2 growth process via a geometric model of the MoS2 flake shape, is developed, which can provide further guidance for the synthesis of 2D materials.

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The 2D van der Waals crystals have shown great promise as potential future electronic materials due to their atomically thin and smooth nature, highly tailorable electronic structure, and mass production compatibility through chemical synthesis. Electronic devices, such as field effect transistors (FETs), from these materials require patterning and fabrication into desired structures. Specifically, the scale up and future development of “2D”-based electronics will inevitably require large numbers of fabrication steps in the patterning of 2D semiconductors, such as transition metal dichalcogenides (TMDs). This is currently carried out via multiple steps of lithography, etching, and transfer. As 2D devices become more complex (e.g., numerous 2D materials, more layers, specific shapes, etc.), the patterning steps can become economically costly and time consuming. Here, we developed a method to directly synthesize a 2D semiconductor, monolayer molybdenum disulfide (MoS2), in arbitrary patterns on insulating SiO2/Si via seed-promoted chemical vapor deposition (CVD) and substrate engineering. This method shows the potential of using the prepatterned substrates as a master template for the repeated growth of monolayer MoS2 patterns. Our technique currently produces arbitrary monolayer MoS2 patterns at a spatial resolution of 2 μm with excellent homogeneity and transistor performance (room temperature electron mobility of 30 cm2 V−1 s−1 and on–off current ratio of 107). Extending this patterning method to other 2D materials can provide a facile method for the repeatable direct synthesis of 2D materials for future electronics and optoelectronics.