The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper: An experimental method is presented in which the proportion of bit pips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally estimated to be between 0.7 . for a custom designed CMOS circuit. Very few multipLe bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.and 2 .
The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states (X) which are likely to propagate to the outputs, causing an overly optimistic coverage estimation of test set efficiency. A new method is presented that is efficient and well-suited for modeling switch-level networks when undetermined states are common. The novel concept of state dominance introduced in this paper is an improvement upon the well-known principle of dominance. The state dominance defines a dynamic direction of signal flow between neighboring nodes of undetermined logic state. A signal transformation scheme is proposed which solves bidirectional conflicts that may occur between adjacent nodes of undetermined logic state without any network recomputation. The new concept is easily applicable to switch-level algorithms in which there is a distributed approach. Int~oductionSwitch-level modeling and simulation have become an important method for predicting the behavior of MOS circuits under the presence of faults. In the design phase, simulation-based fault injection can be used to estimate fault coverage, error detection latency, system reconfiguration time and diagnosability.Most work on simulation-based fault injection and fault simulation has focused on gate-level fault models. However, the classic stuck-at logical fault model is not appropriate for modeling real failures which occur in MOS circuits [l] [2], such as various shorts between metal lines, shorts between gates and the body (gate oxide breakdown) or breaks in metal lines. When predicting the behavior of circuits in the presence of realistic faults, switch-level modeling offers many advantages. By operating directly on the transistor network, switch-level simulators can reliably *) This work was founded by the Swedish National Board for Industrial and Technical Development (NUTEK). model many important phenomena in MOS circuits, such as bidirectional signal propagation, charge sharing and variations in driving strengths [3]-[ 111. When realistic faults are introduced in switch-level descriptions of CMOS networks, steady-state undetermined node values (X) frequently occur in the networks. These undetermined node states arise either as an effect of intermediate transistor gate voltage values or in sitnations in which there are signal paths of equal resistance from both V D D and Gnd. Other phenomena occuring in faulty circuits are feedback bridging faults (which may cause the circuit to oscillate), unwanted charge sharing or timing faults. As undetermined node values are uncommon in the steady-state response of fault-free CMOS networks [ 121, most switch-level simulators do not handle undetermined values in a consistent and efficient way. Most earlier work on switch-level modeling has focused on efficient algorithms that handle situations in which undetermined states are rare. The handling of undetermined values is often pessimistic, which re...
This study evaluates temperatures measured at district heating (DH) valves in manholes and their usability for non-destructively assessing the thermal performance of buried DH pipes. The study was conducted as a field test in which part of a DH network was shut down and the temperature decline in the valves was analysed in terms of absolute temperature and thermal response time from the DH pipe to the top of the valve. The calculated and measured supply pipe temperatures by the drainage valves were in good agreement, with 1% deviation. The valve measurement analysis from this study shows that the drainage valve has good potential to serve as a measurement point for assessing the thermal status of a DH network. However, the shutdown valve measurements were greatly affected by the manhole environment.
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