On latching probability of particle induced transients in combinational networks

Abstract

The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper: An experimental method is presented in which the proportion of bit pips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally estimated to be between 0.7 . for a custom designed CMOS circuit. Very few multipLe bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.and 2 .

Circuit Reliability Analysis Using Symbolic Techniques

“…Intensive research has been done so far in the area of analysis and modeling transient faults [3][4][5][7][8][9]. However, for estimating the likelihood of soft errors as the result of a SEU, most of the previous work has relied on fault injection [1,6,7] and simulation instead of the symbolic modeling of the probability of soft errors.…”

Design of a soft-error robust microprocessor

“…Past research has shown that combinational logic is much less susceptible to allow SEs than memory elements (LIDÉN et al, 1994;GAISLER, 1997). The memories always were considered most vulnerable to SEs due to their spatial density and the amount of information that they store (MAHESHWARI; KOREN; BURLESON, 2003).…”

Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

“…Faults affecting combinational logic may not manifest as an error in the system because the affected combinational signal either i) traverses logic gates with other inputs in their controlling state (logical masking), or ii) is outside the latching windows of all the FFs in the path (temporal masking), or iii) is attenuated by the limited bandwidth of the technology (electrical masking) [112].…”

“…This effect is related to three different intrinsic masking mechanisms [112] previously explained in Section 6.2.2. Pulses seem to be of increasing importance in deep-submicron manufactured systems [117].…”

“…On one hand, faults targeting combinational logic may be masked by any of the three masking mechanism previously presented [112] thus reducing their failure rate. On the other hand, registers may memorise errors that could manifest later as failures which obviously increases their latent or failure rate.…”