Efficient modeling of switch-level networks containing undetermined logic node states

Abstract

The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states (X) which are likely to propagate to the outputs, causing an overly optimistic coverage estimation of test set efficiency. A new method is presented that is efficient and well-suited for modeling switch-level networks when undetermined states are common. The novel concept of state dominance introduced in this paper is an improvement upon the well-known principle of dominance. The state dominance defines a dynamic direction of signal flow between neighboring nodes of undetermined logic state. A signal transformation scheme is proposed which solves bidirectional conflicts that may occur between adjacent nodes of undetermined logic state without any network recomputation. The new concept is easily applicable to switch-level algorithms in which there is a distributed approach. Int~oductionSwitch-level modeling and simulation have become an important method for predicting the behavior of MOS circuits under the presence of faults. In the design phase, simulation-based fault injection can be used to estimate fault coverage, error detection latency, system reconfiguration time and diagnosability.Most work on simulation-based fault injection and fault simulation has focused on gate-level fault models. However, the classic stuck-at logical fault model is not appropriate for modeling real failures which occur in MOS circuits [l] [2], such as various shorts between metal lines, shorts between gates and the body (gate oxide breakdown) or breaks in metal lines. When predicting the behavior of circuits in the presence of realistic faults, switch-level modeling offers many advantages. By operating directly on the transistor network, switch-level simulators can reliably *) This work was founded by the Swedish National Board for Industrial and Technical Development (NUTEK). model many important phenomena in MOS circuits, such as bidirectional signal propagation, charge sharing and variations in driving strengths [3]-[ 111. When realistic faults are introduced in switch-level descriptions of CMOS networks, steady-state undetermined node values (X) frequently occur in the networks. These undetermined node states arise either as an effect of intermediate transistor gate voltage values or in sitnations in which there are signal paths of equal resistance from both V D D and Gnd. Other phenomena occuring in faulty circuits are feedback bridging faults (which may cause the circuit to oscillate), unwanted charge sharing or timing faults. As undetermined node values are uncommon in the steady-state response of fault-free CMOS networks [ 121, most switch-level simulators do not handle undetermined values in a consistent and efficient way. Most earlier work on switch-level modeling has focused on efficient algorithms that handle situations in which undetermined states are rare. The handling of undetermined values is often pessimistic, which re...

Soft error injection using advanced switch-level models for combinational logic in nanometer technologies

“…In switch-level models, an NMOS (PMOS) may be in three different states: It is ON when its gate terminal takes the value 1 (0 for PMOS). It is OFF when its gate terminal takes the value 0 (1 for PMOS), and it is in the unknown state when its gate terminal takes the value Z or U [7]. Voltage strength refers to the amplitude of voltage pulse generated due to particle induced electric charge at the point of injection.…”

“…The switch-level is an abstraction level between the gate level and the electrical level and offers many advantages. By operating directly on the transistor network, switch level simulators can reliably model many important phenomena in MOS circuits, such as bidirectional signal propagation, chargesharing and variations in driving strengths [6]- [7]. Most of the switch-level models used so far neglect the stray capacitance associated with the transistor nodes [8].…”

Modeling of intermediate node states in switch-level networks

“…The number of discrepancies observed is shown in Table IV. As a comparison, identical fault simulations were carried out with another switch-level simulator, BiDom [13], which has an efficient masking capability for handling the X state. However, there is neither an intermediate logic state nor a two-dominance model included in that simulator.…”

“…AN EXTENDED NODE STATE To represent the state of a node assigned the logic state L or H, the traditional single-strength node state, < L, R >, represented by a logic state, L, and a single resistance, R, is adopted. The treatment of nodes assigned the X state is performed according to [13] in which a new (secondary) node state is defined as the state obtained when the node is re-evaluated with the strongest signal driving the X state excluded. It is possible to reduce the spread of X states using this secondary node state.…”

“…In the model proposed in [10], which is based on Kirchoff's laws, no intermediate state is necessary and, in [2], a logic state corresponding to an intermediate voltage interval is proposed. The algorithm proposed in this paper, on the other hand, is based on a local approach [1][11]- [13] in which only a single node and its interaction with neighboring nodes are considered at one time. During the node evaluation procedure, the state of a node is predicted and events are generated and put in a time ordered list whenever there is a change in the predicted state in comparison with the current state of the node.…”