Verification and fault synthesis algorithm at switch-level

Javaheri, M. Reza; Sedaghat, Reza; Kant, Leo; Zalev, Jason

doi:10.1016/j.micpro.2005.12.002

“…In previous research, [32] a novel fault synthesis algorithm for modelling CMOS circuits with an arithmetic solution for circuit verification and fault synthesis was introduced. This new approach is capable of simulating multiple fault injections into the circuit and speeds up switchlevel simulation.…”

Section: A Quick Review Of Fault Propagation In Transistor-levelmentioning

confidence: 99%

“…In the algorithm presented here, a graph model converts a transistor level model to a graph and is independent of circuit complexity. This graph model simplifies the use of the algorithm and fault injection[32][43][44]. In the graph model, nodes represent a transistor or a connection and the edges represent wires.…”

mentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

0

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Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

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“…In previous research, [32] a novel fault synthesis algorithm for modelling CMOS circuits with an arithmetic solution for circuit verification and fault synthesis was introduced. This new approach is capable of simulating multiple fault injections into the circuit and speeds up switchlevel simulation.…”

Section: A Quick Review Of Fault Propagation In Transistor-levelmentioning

confidence: 99%

“…In the algorithm presented here, a graph model converts a transistor level model to a graph and is independent of circuit complexity. This graph model simplifies the use of the algorithm and fault injection[32][43][44]. In the graph model, nodes represent a transistor or a connection and the edges represent wires.…”

mentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

0

View full text Add to dashboard Cite

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

show abstract

A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies

Javaheri

¹

,

Sedaghat

²

2008

Communications in Computer and Information Science

0

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Verification and fault synthesis algorithm at switch-level

Cited by 6 publications

References 25 publications

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies

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