In this study, a physics-based compact model for high speed buffer layer insulated gate bipolar transistor (IGBT) is proposed. The model utilizes the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. Based on the improved understanding on the inductive switching behavior of high speed buffer layer IGBT, the ADE is solved for all injection levels instead of high-level injection only as usually done. Assuming high-level injection condition in the buffer layer, the excess carrier transport, redistribution and recombination in the buffer layer are redescribed. Moreover, some physical characteristics such as the low conductivity of N-base at turn-on transient and free holes appeared in the depletion layer during turn-off process are also considered in the model. Finally, The double-pulse switching tests for a commercial field stop (FS) IGBT and a light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) are used to validate the proposed model. The simulation results are compared with experiment results and good agreement is obtained.Index Terms-insulated gate bipolar transistor (IGBT), power semiconductor modeling, field stop (FS) IGBT, light punchthrough (LPT) carrier stored trench bipolar transistor (CSTBT), physics-based IGBT model.

This paper presents a comprehensive investigation on the self-sustained oscillation of silicon carbide (SiC) MOSFETs. At first, based on the double pulse switching test, it is identified that the self-sustained oscillation of SiC MOSFETs can be triggered by two distinct test conditions. To investigate the oscillatory criteria of the two types of self-sustained oscillation, a small-signal ac model is introduced to obtain the transfer function of the oscillatory system. The instability of the oscillation is thereby determined by the two conjugate pole pairs of the transfer function. By analyzing the damping ratios of the two pole pairs, the parametric sensitivity of various circuit and device’s parameters on the two types of self-sustained oscillation are obtained. The analyses reveal the oscillatory criteria of the self-sustained oscillation for SiC MOSFETs. Based on the oscillatory criteria, necessary methods are proposed to prevent the oscillation. The proposed oscillation suppression methods are validated by the experiment at the end of the paper.

This paper presents a comprehensive study on the occurrence mechanism, instability analysis and suppression methods of self-sustained turn-off oscillation which occurs on cascode gallium nitride high electron mobility transistors (cascode GaN HEMTs). In the beginning, the oscillation waveforms are analyzed, which indicate that the occurrence of the oscillation is determined by test circuit instability. Based on the double pulse test, the impact of the load current IL, DC-bus voltage VDC and gate resistance RG on the self-sustained oscillation is identified. To investigate the instability of the resonant circuit, a smallsignal ac model of the resonant circuit is derived. Based on the model, the influences of various parameters on the self-sustained oscillation are analyzed. The analyses reveal the possible methods which can suppress the oscillation. The effectiveness of the proposed methods is validated by the experimental data and simulation results in the end.

A generalized statistical model is introduced in the paper to qualify the reliability of a dormant system which has multiple de-pendent performance characteristics (PCs). In the model, the univariate degradation process of each PC is governed by Wiener processes with time transformation, and multivariate copula function is used to describe the dependence among the PCs. The parameters of Wiener process and copula function in the model are supposed to depend on temperature and their relationship can be expressed by the transformation functions. Based on the CSADT data, the parameters in the model can be calculated by the maximum likelihood estimate. Then the transformation functions can be derived from these estimated values by the regression analysis. Particularly, as the storage temperature is not constant, the variation of the temperature is taken into consideration in the model. In the end, as an illustration for the given model, a case application is presented as an example.

Purpose The purpose of this paper is to present a failure analysis of the solder layer in a Darlington power transistor in a TO-3 package. Design/methodology/approach A failed Darlington power transistor in a TO-3 package was examined by different kinds of failure analysis techniques. At first, internal gas analysis was conducted to measure the atmosphere. Then, scanning acoustic microscopy (SAM) was performed to check the quality of the solder layers in the failed device, and the failure location was determined in the solder layer between chip and substrate. Next, the failed device was decapped to observe the defects. After removing the chip from the substrate, energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were applied and the main elemental composition of the solder layer was identified. Findings Internal gas analysis indicated that the moisture and oxygen contents exceeded the allowed maximum value. Large areas of voids were found in the solder layer by SAM. The main elemental compositions of the solder layer were identified by scanning electron microscopy and EDS. Furthermore, the valences of the chemical components in the solder layer were identified by XPS. Except for the few simple substances of the initial solder material, the chemical formulae of oxidation products in the solder layer were deduced. In addition, the root causes are also discussed. Originality/value This paper focuses on the solder layer failure of a power transistor. Factors such as the presence of oxygen, voids and other factors, which can cause transistor damage, were comprehensively analyzed. The analysis process is worth learning from and the results can be used to improve the reliability of power devices in this kind of package.

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An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.