We describe a liner' for Cu-Damascene multilevcl ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects'. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (a-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and Nz sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (-30-60 M-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects. Introduction Many liners have been implemented in experimental Cu integration schemes. The family of Ta-based compounds has emerged prominently. Ta (P-phase) was first shown to be an excellent Cu diffusion barrier in 1986 by Hu et d 3 . It was since found4 that a low background level (e.g. < l o 7 Torr) of O2 or H 2 0 was responsible for decreasing Cu diffusivity through Ta grain boundaries. (Presumably, current studies that fmd reduced Ta barrier performance stem fiom the low base pressures of modem PVD systems, and could be helped by a controlled leak of 02.) Such a P-Ta(0) barrier was used in the first multilevel Cu integration in polyimide ILD', due to its optimal adhesion to the materials used6. For dualDamascene integration in Si022 however (see fig. 1 .), Ta and Ta2N7 lack adequate adhesion to SO2, whereas TaN/SiO2 adhesion is excellent ( fig. 2). On the other hand, Cu/TaN adhesion is relatively poor. In fact, the liner/ILD and Cdliner adhesion have conflicting dependencies on N% in TaN,. We believe it is essential to maximize adhesion at all interfaces, especially the Cu/liner one. This is both to resist delamination during processing or thermal stressing, and for electromigration resistance in fine Cu lines, where interfacial and surface migration play a large role*. As confirmed elsewhere', Cu E-M lifetimes are lower when against a TaN vs. a Ta liner. Unlike CdTaN, /W, and /TiN, the CdTa interface exhibits high wetting" and atomic-scale mixing". This occurs without alloying, which would consume Cu atoms. The Cu/Ta interface is thus uniquely optimal among the commonly studied candidates.Another essential liner quality which has not been addressed generally elsewhere and which is lacking in TaN or TiN, is the capacity for current-strapping (electromigration rcdundancy) by a suitably thin liner. In thc event of Cu defects or elcctromigration wearout, a propcr liner should prevent or dclay open-circuit failurc, cvcn at maximum rated currcnt concentrated in the liner. Such rcdundancy is achieved by the TiAh alloy ovedunder cladding in our AI(Cu) interconnects, and is a reliability requirement for our Cu interconnccts as well. DiscussiodData Our evaluation factors for designing a Cu Damascenc liner are shown in Table I, with results from screening of many candidat...
This paper summarizes the adhesion test standard and technique developed collectively by groups from the IBM Research Division, Yorktown Heights, and the Development Laboratory of IBM Microelectronics Division at East Fishkill. This activity was initiated since the increased complexity of interconnection technologies require a large number of interfaces to maintain their integrity while being subjected to a large variety of processes. For example, reliable adhesion of polymer layers to metals and ceramics plays a vital role in several IBM key product technologies, such as the recently announced Glass-Ceramic Module multichip packaging technology used in the system 390ES9000, models 820, 900 and 9021, computers and the Metallized Ceramic Polyimide (MCP) products. During the course of these product development cycles, it was noted that, sample preparation and measurement techniques can strongly affect the measured adhesion strength of a multi-component structure such as that found in multichip and multilayer modules. As a result of the observed variability in a multitude of adhesion measurements from many IBM laboratories, it was decided that standardization of the sample preparation and adhesion measurement techniques was required. During the course of collective work between a large number of participants, it became clear, that once a certain number of rules are followed, data collected from different workers can be compared. These rules form the basis of the peel standard which is discussed here. Once the standard measurement of adhesion is implemented, various adhesion promotion techniques can be directly compared, which lead to a swift and facile improvement in the reliability of products and in their development cycle time.
With wireless communications becoming an important technology and growth engine for the semiconductor industry, many semiconductor companies are developing technologies to differentiate themselves in this area. One means of accomplishing this goal is to find a way to integrate passive components, which currently make up more than 70% of the discrete components in a wireless handset, directly on-chip thereby greatly simplifying handsets. While a number of technologies are being investigated to allow on-chip integration, microelectromechanical systems technologies are an important part of this development effort. They have been used to create switches, filters, local oscillators, variable capacitors, and high-quality inductors, to name a few examples. The lithography requirements for these devices are very different than those found in standard semiconductor fabrication with the most important involving patterning over extreme topography. We discuss some of the fabrication challenges for these devices as well as some approaches that have been demonstrated to satisfy them.
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