There has been recent awareness of the drastic effects of interconnect delay in VLSI implementations, and several investigations focused on this problem have been linked directly to multiplier structures. The tree, or column compression techniques, used for partial product reduction have the severe impediment of highly irregular interconnections. A digital multiplier architecture will be presented in this paper that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration.Regulated by a 2-bit control signal, the multiplierprovides optimal circuitry for both single and double precision arithmetic, as well as fault tolerant and dual throughput single precision operation. Moreovel; dynamic power management techniques allow f o r 75% power reduction in single precision mode, and 50% power reduction for SlMD applications.
The 4:2 compressor has transformed the standard frame of mind for counter based partial pmduct reduction schemes by introducing the notion of horizontal data paths within stages of reduction. Since its inception by Weinberger in 1981, this concept has soared in popularity in many digital multiplication and multi-operand addition schemes. The application of 4:2 compressors has also been the focus of several studies promoting its use over Booth recoding schemes. This paper provides an in depth look at the 4:2 compressor, and a novel layout scheme for optimal placement will be presented.
This paper explores the effects of truncation schemes in recursive multiplier architectures in terms of the trade-off between circuit complexity versus introduced truncation errors. The recursive architecture is examined due to its inherent hierarchical structure whereby a larger multiplication is subdivided into a collection of smaller multiplications. Three data-dependent truncation schemes are proposed that exploit this multiplication architecture. Error analysis and complexity savings for each scheme are also discussed.
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