A reconfigurable digital multiplier architecture

Abstract

There has been recent awareness of the drastic effects of interconnect delay in VLSI implementations, and several investigations focused on this problem have been linked directly to multiplier structures. The tree, or column compression techniques, used for partial product reduction have the severe impediment of highly irregular interconnections. A digital multiplier architecture will be presented in this paper that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration.Regulated by a 2-bit control signal, the multiplierprovides optimal circuitry for both single and double precision arithmetic, as well as fault tolerant and dual throughput single precision operation. Moreovel; dynamic power management techniques allow f o r 75% power reduction in single precision mode, and 50% power reduction for SlMD applications.

Recursive architectures for 2DLNS multiplication

“…A recursive digital multiplier architecture has been previously presented in [11]. This architecture is also centered on recursive multiplication and includes a new column compression scheme to alleviate interconnection irregularity.…”

“…It has been shown that the most efficient recursive binary multiplier corresponds to only one level of recursion [11]. Since in 2DLNS, the size of RALUTs are exponentially proportional to the size of the second-base exponent, this process may be repeated using even smaller base multipliers, which will be explained in the next section.…”

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier

“…The operand rotating technique was further improved by Townsend et al [19] to reduce the area overhead. Mokrian et al propose a hybrid multiplier architecture [12]. Four Booth-encoded 32-bit multipliers are connected as a recursive multiplier to form a 64-bit multiplier.…”

“…As a result, there is a plethora of fault tolerance techniques [8,5,3,12] which we will discuss in greater detail in Section 2. However, direct application of these techniques to multipliers in commodity microprocessors is limited due to two major concerns.…”

An efficient twin-precision multiplier

“…It is certainly not straightforward to transfer the proposed technique to tree multipliers. Mokrian et al presented a reconfigurable multiplier, which is constituted by several smaller tree multipliers [6]. However, the recursive nature of this multiplier is, due to an addition of reduction stage(s), likely to have a large impact on the delay for the N-b multiplication, compared to the multiplier proposed in this paper.…”