Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier

Abstract-Functional, at-speed vectors continue to provide added value to the testing community as circuit complexity rises. Complex defects may escape traditional scan vectors and thus often require at-speed patterns. However, generation of functional/sequential vectors is an extremely challenging problem. Previous methods rely on formal models of the RTL or calls to gate level ATPG, both of which are computationally expensive, limiting the efficacy of gains made in RTL stimuli generation. In this work, we present an efficient engine for the generation of high quality functional tests at the RTL which are effective for both validation and at-speed defect detection. The proposed method utilizes a rule based, behavioral coverage metric to accurately assess the activation of circuit modules by the generated stimuli. Based on this metric, we are able to effectively generate functional test vectors at the RTL, without additional gate level information, that can achieve a high level of defect coverage and up to an order of magnitude speedup over existing techniques.

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“…The expansion for multiplication is based on a technique for self-verifying multipliers [16] with a low probability of fault escape.…”

Section: ) Operator Coverage Rulesmentioning

confidence: 99%

Fast Multi-level Test Generation at the RTL

Gent

Hsiao

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…On-line testing techniques to detect occurrence of a soft fail is necessary to enable architectural solutions like single bit correction and double bit detection via Error Correction Code (ECC), and operational retry procedures after concurrent detection [8] [9]. Operational retry is also utilized by Yilmaz et al [10] to test soft vs.…”

Section: Background and Related Workmentioning

confidence: 99%

“…al. also applied the same scheme for distinguishing between soft and hard fail in their fault-tolerant multiplier design [10], it has not been utilized in BIST design for SER characterization.…”

Section: A Pattern Generationmentioning

confidence: 99%

A Built-In Self-Test Scheme for Soft Error Rate Characterization

Sanyal¹,

Alam²,

Kundu

2008

2008 14th IEEE International on-Line Testing Symposium

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Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for extended period of time. While built-in self-test (BIST) mechanisms have been around for over a decade, that minimizes the use of a tester; they have not been applied to measure or characterize soft error rate. This is because traditional BIST methods cannot distinguish between a soft failure and a hard failure and have no provision for counting the number of errors. In this paper, we propose a BIST design for soft error rate (SER) characterization, which obviates those issues. The proposed BIST based SER measurement scheme can be further accelerated by improved controllability and observability while unlike traditional BIST schemes, a test by test failure detection capability enables higher diagnostic resolution for single event based transient errors. We further propose to integrate this chip-level BIST-based SER characterization system with a distributed on-line scheme using a network controller that tests multiple chips in parallel and completely eliminates the need for a tester. The hardware overhead of the proposed architecture is small and it becomes insignificant for larger design.

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“…This scheme includes a totally self-checking, 2-rail checker which can detect all faults except the ones in the primary inputs and primary outputs. Yilmaz et al [28] detect errors in a recursive multiplier by using a modulo-3 checker. The authors report 26% area overhead and almost 99% fault coverage for this scheme.…”

Section: Options For Error Detectionmentioning

confidence: 99%

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor

Ozev

Sorin

Yilmaz

2007

2007 25th International Conference on Computer Design

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This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only relevant fault model. The delay fault model --which assumes that the faulty circuit element gets the correct value but that this value arrives too late -encompasses many of the actual in-field wearout faults in modern microprocessors. In-field wearout faults, such as time-dependent dielectric breakdown and electromigration, cause signal propagation delays which may be missed during production test time. These defects progress exponentially over time, potentially causing a catastrophic failure. Our goal is to diagnose hard delay faults (i.e., identify them as hard faults, not transients) during run-time before they lead to catastrophic chip failures. Results show that we can diagnose all injected delay faults and that prior diagnosis mechanisms, which target only stuck-at faults, miss the majority of them.

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Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier

Abstract: In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P)

Cited by 12 publications

References 21 publications

Fast Multi-level Test Generation at the RTL

Fast Multi-level Test Generation at the RTL

A Built-In Self-Test Scheme for Soft Error Rate Characterization

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor

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