On the use of 4:2 compressors for partial product reduction

Mokrian, P.; Howard, G.M.; Jullien, G.A.; Ahmadi, M.

doi:10.1109/ccece.2003.1226358

Cited by 9 publications

(1 citation statement)

References 13 publications

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“…Figure 1(a) shows an exact 4:2 compressor [24] comprises of five inputs and three outputs. Intuitively, exact 4:2 compressors are obtained by cascading two 3:2 full adders, as shown in Figure 1(b).…”

Section: Proposed 4:2 Approximate Compressormentioning

confidence: 99%

Compressor based approximate multiplier architectures for media processing applications

Kumar

Ahmed

2021

IJECE

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Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.

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Section: Proposed 4:2 Approximate Compressormentioning

confidence: 99%