This paper reviews the work carried out under the European ACTS KEOPS (KEys to Optical Packet Switching) project, centering on the definition, development and assessment of optical packet switching and routing networks capable of providing transparency to the payload bit rate. The adopted approach uses optical packets of fixed duration with low bit rate headers to facilitate processing at the network/node interfaces. The paper concentrates on the networking concepts developed in the KEOPS project through a description of the implementation issues pertinent to optical packet switching nodes and network/node interfacing blocks, and consideration of the network functionalities provided within the optical packet layer. The implementation, from necessity, relies on advanced optoelectronic components specifically developed within the project, which are also briefly described.

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Fast-optical packet switching is becoming more and more viable, thanks to both the progress in device technology and in systemlnetwork architectures. In the mainframe of the RACE ATMOS project, a complete rack-mounted 2 X 2 switchingnode demonstrator, called fiber loop memory switch (FLMS), has been developed'? the principle of operation3 relies on fast wavelength assignment (with wavelength converters) at the input; a wavelength-controlled fiber loop memory for cell buffering; and fast tuneable DFB filters4 for cell routing at the node outputs. At the node inputs, the incoming cells are converted to new wavelengths, belonging to a set (four in the demonstrator) coinciding with the gateable narrow band (-10 GHz) optical filters in the fiber loop (loop length = one cell duration): depending on the contention situations occurring, the gateable filters are enabled or disabled, to buffer the cells (by letting them circulate) or to erase the corresponding memory position (Fig. 2). An electronic control reads the incoming cells tags, identifying the output addresses, and consequently manages to drive all optoelectronic devices, solving cell contentions and routing the cells to the desired outputs. The demonstrator ( Fig. 1) operates at 622 Mbit/s, with wavelength spaced by 0.4 nm around 1540 run.In this work the first results of the quantitative assessment of the switch performance are reported. The set-up developed for this purpose is shown, together with a schematic of the FLMS in Fig. 2. It allows a cell-by-cell bit-error-rate (BER) characterization, due to the possibility of isolating one cell in the output sequence by means of an electronic gate on the detected signal, purposely delayed and synchronized with the data pattern. The cell sequence (pattern) for the two FLMS inputs is created by a computer, which programs the data generator, which in turn drives the input transmitters with the repeated data sequence. Different cell collision and buffer filling situations can be created to verify the operation of the electronic WD1 Fig. 1. Improved rack-mounted FLMS demonstrator. Reset Delay synthesizerPanem sync WD1 performance. Fig. 2. Set-up for BER characterization of FLMScontrol and of the whole FLMS. Once the input sequences are created, the expected output cell sequences (at the two FLMS outputs) are determined: in these repeated sequences one cell is chosen for BER measurements. The error counter is programmed to detect a pattern including all zeros, except for the selected cell. First BER measurements have been carried out, as reported in Fig. 3. The penalty for straight-through cells is limited to -1.5 dB. For cells that have been stored in the loop memory, cross talk and noise accumulation cause a slightly increased penalty, of about 3.2 dB. In the figure, the BER is obviously scaled to take into account the small mark/space ratio at the error counter.In conclusion, we have reported the first BER measurement of photonic switch based on a wavelength-controlled fi-

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