A Silicon Photonics Technology for 400 Gbit/s Applications

Bœuf, F.; Monfray, S.; Jan, S.; Deglise, C.; Manouvrier, Jean-Robert; Durand, C.; Simbula, Angelica; Goguet, D.; Bar, P.; Ristoiu, D.; Leverd, F.; Fincato, A.; Babaud, L.; Daverio, Alessio; Binda, Marco; Bazzotti, Adamo; Canciamilla, A.; Ramini, Luca; Traldi, Matteo; Gambini, P.; Maggi, Luca; Carpentier, J.F.; Maître, Patrick Le; Shaw, Mark; Crémer, S.; Vulliet, N.; Baudot, Charles

doi:10.1109/iedm19573.2019.8993627

Cited by 21 publications

(10 citation statements)

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“…In this paper, we experimentally validated two different design paradigms for perfectly vertical dual layer Si+SiN single-polarization GCs: GCs designed using inverse design based on the adjoint method (as proposed in our previous work [11]), and adjoint-inspired GCs (adapting the technique proposed in [36] to the dual layer stack). These devices were fabricated on a hybrid Si/SiN platform using scalable immersion DUV lithography on 300 mm wafers, with critical dimensions (60 nm) for the c-Si layer as well as relatively high aspect ratios (6 : 1) for the SiN features that can be considered state-of-the-art for the silicon photonics community [29][30][31][32][33][34][35]. For both design methodologies, using WLT, for the first time, we experimentally demonstrated record low median IL of 1.3 dB (with interquartile range of ∼0.1−0.2 dB) for perfectly vertical coupling for dual layer device designs that are compatible with volume fabrication, which is ∼0.5 dB better than our previously demonstrated single layer, single-etch c-Si alternative [36].…”

Section: Discussionmentioning

confidence: 99%

“…Both Si and SiN layers are patterned with an advanced DUV immersion lithography with a minimum feature size of 60 nm (100 nm) for the Si layer (SiN respectively). The patterning of the SiN, with these critical dimensions and aspect ratios developed by the foundry [29][30][31], can be considered state-of-the-art when compared with similar platforms currently developed by other foundries [32][33][34][35].…”

Section: Fabrication Of the Dual Layer Si+sin Wafers: Layer Stack Si/...mentioning

confidence: 99%

“…In this paper, we apply advanced design techniques to GC design in an emerging hybrid c-Si/SiN layer stack [29][30][31][32][33][34][35]. Specifically, we investigate perfectly vertical GCs as the 0 deg coupling might simplify the mechanical design of single-mode connectors in datacom or HPC interconnects [3,11].…”

Section: Introductionmentioning

confidence: 99%

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Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

Vaerenbergh¹,

Hooten

Jain

et al. 2022

J. Phys. Photonics

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Recently, silicon photonics foundries started providing access to new dielectric stacks which can be utilized to reduce optical I/O losses. For example, in a hybrid c-Si/SiN platform, inverse design techniques can be used to create novel dual layer grating coupler (GC) designs which, in simulations, reach state-of-the-art performance. In this paper, we experimentally validate such designs for perfectly vertical single-polarization GCs in the O-band consisting of a single-etch c-Si layer with a patterned SiN overlay, fabricated using a 193nm DUV immersion lithography process on 300mm wafers. Here, we investigate designs generated by two different design paradigms: inverse design based on the adjoint method and adjoint-inspired design. Using wafer-level testing, we experimentally demonstrate a record low median insertion loss (IL) of 1.3 dB (with interquartile range of ∼ 0.1 − 0.2 dB) for perfectly vertical coupling in DUV lithography compatible devices which is a ∼ 0.5 dB improvement over previously demonstrated single-layer, single-etch c-Si 0 deg GCs.

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Section: Discussionmentioning

confidence: 99%

Section: Fabrication Of the Dual Layer Si+sin Wafers: Layer Stack Si/...mentioning

confidence: 99%

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Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

Vaerenbergh¹,

Hooten

Jain

et al. 2022

J. Phys. Photonics

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“…Especially, the coarse wavelength-division multiplexing (CWDM) is utilized in today's silicon photonic products such as the 100G CWDM4 QSFP28 optical transceiver and the recently released 400 G optical transceiver using 4-level pulse amplitude modulation (PAM4) by Intel [8]. Recently, there are also many other demonstrations of silicon optical transceivers which are further extending the data transmission speed to more than 400 Gb/s [9][10][11]. Towards 800 G silicon photonic optical modules, there are many viable solutions such as PSM 4 × 200 G, PSM 8 × 100 G, and WDM 8 × 100 G [12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Numerical Demonstration of 800 Gbps WDM Silicon Photonic Transmitter with Sub-Decibel Surface-Normal Optical Interfaces

Zhang

et al. 2022

Micromachines

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We propose and numerically demonstrate an 800 Gbps silicon photonic transmitter with sub-decibel surface-normal optical interfaces. The silicon photonic transmitter is composed of eight silicon Mach–Zehnder optical modulators and an interleaved AMMI WDM device. This WDM device comprises two 1 × 4 angled MMI and a Mach–Zehnder interferometer (MZI) optical interleaver with an apodized bidirectional grating which has about −0.5 dB coupling loss. Both the Mach–Zehnder electro-optical modulators and MZI optical interleaver regard the bidirectional grating coupler as vertical optical coupler and 3-dB power splitter/combiner. By importing the S-parameter matrices of all the components which have been carefully designed in simulation software, the circuit-level model of the optical transmitter can be built up. On this basis, the static and dynamic performance characterization were carried out numerically. For NRZ modulation, the optical transmitter exhibits the overall optical loss of 4.86–6.72 dB for eight wavelength channels. For PAM4 modulation, the optical loss is about 0.5 dB larger than that of NRZ modulation, which varies between 5.38–7.27 dB. From the eye diagram test results, the WDM silicon photonic transmitter can achieve single channel data transmission at 100 Gb/s NRZ data or 50 GBaud/s PAM4 symbol rate with acceptable bit error rate.

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“…Among the required components used on photonic chips, modulators play a key role. The 2 main standards for datacom are transceivers at 25Gb/s with 4 parallel lines to achieve 100Gb/s, and 4x53GBd using PAM-4 for 400Gb/s [1].…”

Section: Introductionmentioning

confidence: 99%

Capacitive Modulator Design Optimization Using Si and Strained-SiGe for Datacom Applications

Charlet

Désières

Marris‐Morini

et al. 2021

IEEE J. Select. Topics Quantum Electron.

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Silicon photonics has become an industrial reality for datacom applications. Nevertheless, as Si suffers from a low electro-optic effect, commercial modulators are few-mm long. The efficiency can be enhanced by using strained-SiGe or by using a semiconductor insulator semiconductor (SIS) architecture. In this paper, we develop a model based on a perturbative approach to optimize capacitive modulator using full-Si or including a thin layer of strained SiGe. This model is coupled with an optimization algorithm in order to estimate the highest optimal modulation amplitude for different operating frequencies.

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A Silicon Photonics Technology for 400 Gbit/s Applications

Cited by 21 publications

References 0 publications

Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

Numerical Demonstration of 800 Gbps WDM Silicon Photonic Transmitter with Sub-Decibel Surface-Normal Optical Interfaces

Capacitive Modulator Design Optimization Using Si and Strained-SiGe for Datacom Applications

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