Formation of pitting at copper-contaminated sites on the silicon wafer surface during immersion in dilute hydrofluoric acid solution is elucidated by atomic force microscopy observations and electrochemical methods. It was discovered that the pit formation was promoted by the absence of light and hindered under illumination, irrespective of the conductivity type of silicon. From electrochemical measurement of voltammetry, the system was found to form a corrosion-type redox couple, composed of the anodic dissolution of silicon and the cathodic reduction of hydrogen ions, where the later reaction is enhanced by the presence of copper on the silicon surface. In addition, under illumination, either the cathodic or anodic reaction is enhanced, depending on the conductivity type of silicon due to a large increase in minority carrier concentration due to illumination. For creation of a localized pit, formation of the localized redox couple between copper and the nearby silicon surface is essential. This reaction is allowed under the darkened condition, but is obscured by the overwhelming amount of carriers generated under illumination.

The iron-related deep levels in n-type silicon and their thermal stabilities were investigated by deep-level transient spectroscopy (DLTS). Three deep energy levels at E c − 0.35, E c − 0.41, and E c − 0.48 eV were observed and classified into two types from the annealing behavior at room temperature and a low temperature of 200 °C. We found for the first time that only one iron-related deep level at E c − 0.35 eV was highly stable at room temperature and 200 °C, while other iron-related deep levels were unstable. We also found that the concentration of the deep energy level at E c − 0.41 eV gradually decreased at room temperature. These results suggest that the origin of the thermally stable level at E c − 0.35 eV is attributed to the substitutional iron-related level, and those of the thermally unstable levels at E c − 0.41 and E c − 0.48 eV are attributed to interstitial iron-related complexes such as iron-acceptor pairs in p-type silicon.

The surface roughness of silicon wafer is one of the most important issues that degrade characteristics of semiconductor devices. The importance of spatial roughness frequency as an influential parameter has been pointed. In this research, the effect of roughness frequency on MOSFET characteristics was studied using samples with different roughness for frequency. From the obtained results, it was found that roughness with a low spatial wavelength affects electron mobility and gate insulating film reliability such as E bd, Q bd and SILC.

Thermally activated defect behaviors in nitrogen (N)-doped Czochralski silicon (Cz-Si) single crystals were investigated using deep level transient spectroscopy and quasi-steady-state photoconductance to confirm the crystals’ applicability in insulated gate bipolar transistors (IGBTs). The thermally activated defects, which were probably N-vacancy complexes and degraded the minority carrier lifetime, were detected with extremely low densities in N-doped Cz-Si compared with N-rich floating zone Si single crystals after heat treatments at 500 °C, resulting in a high remaining value of minority carrier lifetime. The difference was assumed to come from whether vacancies were released in the Si matrix during heat treatment. For the Cz-Si, vacancies were assumed to be strongly bound with oxygen atoms with concentrations of 1017 atoms cm−3. Therefore, vacancies were not released during heat treatment, resulting in low remaining N-vacancy complex densities. N-doped Cz-Si are potential materials for IGBTs because of their low densities from thermally activated defects.

Nitrogen-doped silicon wafers manufactured using the Czochralski technique (Cz-Si) with an oxygen concentration ([OI]) of 2.5-5.6 × 10 17 atoms cm −3 are heat treated to simulate the conventional and scaled manufacturing processes of insulated gate bipolar transistors (IGBTs). Subsequently, the oxygen precipitation, lifetime, and gate oxide integrity (GOI) of the Cz-Si wafers are evaluated. After the high-temperature heat treatment that simulates the conventional process, the lifetime of the Cz-Si with an [OI] of 5.6 × 10 17 atoms cm −3 only degrades slightly even when oxide precipitates are not detected. In contrast, after the lowtemperature heat treatment that simulates the scaled process, oxide precipitates are detected and the lifetime reduces substantially at an [OI] of 5.6 × 10 17 atoms cm −3 . The Cz-Si with [OI] values below 3.3 × 10 17 atoms cm −3 are considered suitable materials for IGBTs because no oxide precipitate is formed, and the lifetime is not degraded after high-and low-temperature heat treatments. Upon using GOI evaluation, the nitrogen-doped Cz-Si wafers are found to exhibit a breakdown voltage equal to that of an annealed Cz-Si wafer conventionally used for IGBTs. Therefore, nitrogen-doped Cz-Si wafers with [OI] below 3.3 × 10 17 atoms cm −3 are potential materials for conventional and scaled IGBTs.