Switched capacitors (SCs)-based modules are being increasingly used for multilevel DC to AC power conversion, especially for low input voltage applications. Many of these topologies operate in two stages involving H-bridge switches, which endure high-voltage stress. The SC 9-level module (SC9LM) presented here operates in a single stage with one DC source and two capacitors. In addition, the peak inverse voltage of all power switches is confined to the voltage of the input DC source. The proposed 9-level module ensures a reduced number of power switches. In addition, with appropriate utilisation of states, two of the eleven switches in the module operate at fundamental switching frequency, thereby minimising the switching losses. A single SC9LM achieves a voltage gain of two. The proposed module is validated through circuit analysis followed by simulation and experimental results.

Multilevel inverters (MLIs) are rapidly acquiring techno-economic feasibility for both high-power and medium-power applications. Increased number of power switches has been cited as one of the most important limitations of MLIs; and to overcome it, a whole new class of MLI topologies has come up. These topologies are commonly called 'reduced device count' MLIs (RDC-MLIs). As the number of controlled switches is significantly reduced in RDC-MLIs, the redundant states are also reduced. Hence, the possibility of fault tolerant operation is severely affected. This study looks at the possibility of imparting fault-tolerant characteristics to RDC-MLIs. In this study, some of the recently proposed RDC-MLI topologies are first analysed for the possibility of fault tolerant operation in the case of 'any single switch open-circuit fault (ASSOF)'. Thereafter, an optimal addition of power switch is proposed which enables fault tolerant operation in the event of ASSOF. Furthermore, these modified RDC-MLIs are verified under normal and faulty conditions using software simulations and experimental setups and these results are presented.

A major disadvantage of two-stage topologies of switched capacitors based multilevel inverters is the use of H-bridge switches which endure high peak-inverse-voltage (PIV). In such topologies, the H-bridge stage is preceded by a levelgeneration stage which synthesises unipolar voltage levels. In this work, a bi-polar module is proposed which can synthesise nine levels at the AC terminals with a single DC input. The proposed module uses power switches with PIV equal to that of the input DC source. Use of switched capacitors in each of the proposed module enables a voltage gain of two. Such bi-polar voltage-doubler modules can be easily connected in a cascaded fashion to increase the number of levels, without involving Hbridge switches. Working modes of the module ensure that the capacitors are self-balanced. A complete analysis of the proposed module is presented. Also, experimental results are presented for validation. In addition, a comparison with other topologies has been presented.

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Summary Reliability and large number of components are major challenges for multilevel inverters being used in many industrial applications. These inverters may face situations like failure of power switches, which, in turn, can cause severe damage to other equipment of the system. Hence, it is important these inverters are fault‐tolerant. In this article, some of the recently proposed reduced device multilevel inverter (RD‐MI) topologies are considered and analyzed in light of imparting open circuit fault‐tolerance capability. In RD‐MIs, the occurrence of faults would cause a shutdown of the system due to the lack of redundant switching states. However, for the cases involving “any single open‐switch failure (SOSF),” the system can continue to operate uninterrupted by imparting fault‐tolerant (FT) feature to the RD‐MIs. With the proposed solution, the complete system shutdown can be avoided, thereby achieving higher reliability. In this work, two RD‐MIs are chosen to demonstrate the proposed approach. Further, the proposed FT RD‐MIs based on suggested FT strategy under the healthy and abnormal modes are simulated using MATLAB/Simulink software. The obtained simulation results are experimentally validated.