5A silicon particle-telescope system for light-ion nuclear reactions is described. In particular, the system is optimized for level density and γ-ray strength function measurements with the so-called Oslo method. Eight trapezoidal modules are mounted at 5 cm distance from the target, covering 8 forward angles between θ = 40 and 54 • . The thin front ΔE detectors (130 μm) are segmented into eight pads, determining the reaction angle θ for the outgoing charged ejectile. Guard rings on the thick back E detectors (1550 μm) guarantee low leakage current at high depletion voltage.

3D-detectors, with electrodes penetrating through the entire substrates have drawn great interests for high energy physics and medical imaging applications. Since its introduction by C. Kenney et al in 1995, many laboratories have begun research on different 3D-detector structures to simplify and industrialise the fabrication process. SINTEF MiNaLab joined the 3D collaboration in 2006 and started the first 3D fabrication run in 2007. This is the first step in an effort to fabricate affordable 3D-detectors in small to medium size production volumes. The first run was fully completed in February 2008 and preliminary results are promising. Good p-n junction characteristics have been shown on selected devices at the chip level with a leakage current of less than 0.5 nA per pixel. Thus SINTEF is the second laboratory in the world after the Stanford Nanofabrication Facility that has succeeded in demonstrating full 3D-detectors with active edge. A full 3D-stacked detector system were formed by bump-bonding the detectors to the ATLAS readout electronics, and successful particle hit maps using an Am-241 source were recorded. Most modules, however, showed largely increased leakage currents after assembly, which is due to the active edge and pspray acting as part of the total chip pn-junction and not as a depletion stop. This paper describes the first fabrication and the encountered processing issues. The preliminary measurements on both the individual detector chips and the integrated 3D-stacked modules are discussed. A new lot has now been started on p-type wafers, which offers a more robust configuration with the active edge acting as depletion stop instead of part of the pn-junction.

Abstract-As predicted by the ITRS roadmap, semiconductor industry development dominated by shrinking transistor gate dimensions alone will not be able to overcome the performance and cost problems of future IC fabrication. Today 3D integration based on through silicon vias (TSV) is a wellaccepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. Several full 3D process flows have been demonstrated, however there are still no microelectronic products based on 3D TSV technologies in the market -except CMOS image sensors. 3D chip stacking of memory and logic devices without TSVs is already widely introduced in the market. Applying TSV technology for memory on logic will increase the performance of these advanced products and simultaneously shrink the form factor. In addition to the enabling of further improvement of transistor integration densities, 3D integration is a key technology for integration of heterogeneous technologies. Miniaturized MEMS/IC products represent a typical example for such heterogeneous systems demanding for smart system integration rather than extremely high transistor integration densities. The European 3D technology platform that has been established within the EC funded e-CUBES project is focusing on the requirements coming from heterogeneous systems. The selected 3D integration technologies are optimized concerning the availability of devices (packaged dies, bare dies or wafers) and the requirements of performance and form factor. There are specific technology requirements for the integration of MEMS/NEMS devices which differ from 3D integrated ICs (3D-IC). While 3D-ICs typically show a need for high interconnect densities and conductivities, TSV technologies for the integration of MEMS to ICs may result in lower electrical performance but have to fulfill other requirements, e. g. mechanical stability issues. 3D integration of multiple MEMS/IC stacks was successfully demonstrated for the fabrication of miniaturized sensor systems (e-CUBES), as for automotive, health & fitness and aeronautic applications.

Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable-B-Layer and High Luminosity LHC (HL-LHC)) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS Inner Detector solenoid field. Sensors were bump bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

High-density through-wafer interconnects are of great interest for fabricating real 3D microsystems. A complete solution for realizing through-wafer interconnects is presented. The proposed solution is believed to be cost effective and easy to integrate in a device process flow. A deep reactive ion etch process was developed to etch 20 × 20 µm2 via holes through 300 µm thick silicon wafers. Thermal oxide is used to insulate the vias from the bulk silicon and heavily doped polysilicon is used as the conductor. Aluminum metallization is provided on both sides of the wafer. The electrical resistance of a single through-wafer via is close to 30 Ω.

Silicon sensors with a three-dimensional (3-D) architecture, in which the n and p electrodes penetrate through the entire substrate, have many advantages over planar silicon sensors including radiation hardness, fast time response, active edge and dual readout capabilities. The fabrication of 3D sensors is however rather complex. In recent years, there have been worldwide activities on 3D fabrication. SINTEF in collaboration with Stanford Nanofabrication Facility have successfully fabricated the original (single sided double column type) 3D detectors in two prototype runs and the third run is now on-going. This paper reports the status of this fabrication work and the resulted yield. The work of other groups such as the development of double sided 3D detectors is also briefly reported.

No abstract

The Pixel detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider (LHC), and plays a key role in the reconstruction of the primary and secondary vertices of short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology is an innovative combination of very-large-scale integration (VLSI) and MicroElectro-Mechanical-Systems (MEMS) where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradiated 3D devices produced at FBK (Trento, Italy). The performance of these devices, all bump-bonded with the ATLAS pixel FE-I3 readout chip, is compared to that observed before irradiation in a previous beam test.