Development of cost-effective high-density through-wafer interconnects for 3D microsystems

Lietaer, Nicolas; Storås, Preben; Breivik, L.; Moe, Sigurd

doi:10.1088/0960-1317/16/6/s06

Cited by 24 publications

(10 citation statements)

References 4 publications

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“…The most common materials used as conductive layers are copper and doped polysilicon due to their favorable deposition properties-copper electroplating or Chemical Vapor Deposition (CVD) of the polysilicon (Premachandran et al 2003;Lietaer et al 2006). Anyway, for some applications (like RF MEMS), gold fillings seems to be the best choice to avoid problems like contamination (for copper) or large resistivity (for polysilicon).…”

Section: Introductionmentioning

confidence: 99%

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

Vasilache

Colpo²,

Giacomozzi³

et al. 2012

Microsyst Technol

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This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via's with a good control over the walls angles for two etching windows sizes (100 and 20 lm respectively) on 300 lm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3°and 21.8°. Barrier and seed layers were deposited in via's performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via's.

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Section: Introductionmentioning

confidence: 99%

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

Vasilache

Colpo²,

Giacomozzi³

et al. 2012

Microsyst Technol

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show abstract

“…1 TSVs are fabricated by deep reactive-ion etching (DRIE) of Si to form via trenches, 9,10 often followed by deposition of a side-wall diffusion barrier, typically silicon oxide or titanium nitride, followed by deposition of the metal, either copper by plating onto a seed layer, or poly-Si or tungsten (W) by chemical vapor deposition (CVD). [11][12][13][14] Typical via dimensions are a few micrometers in width and many tens of micrometers in length through the substantially thinned Si die.…”

Section: Introductionmentioning

confidence: 99%

Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via

Koseski

Osborn

Stranick

et al. 2011

Journal of Applied Physics

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The stress in silicon surrounding a tungsten-filled through-silicon via (TSV) is measured using confocal Raman microscopy line scans across the TSV both before and after etch removal of an oxide stack used as a mask to define the TSV during fabrication. Stress in the silicon arose in response to both athermal deposition and thermal expansion mismatch effects. The complex three-dimensional stress and strain field in silicon surrounding the TSV is modeled using finite element analysis, taking into account both athermal and thermal effects and the elastic anisotropy of silicon. Comparison of the measurements and model results shows that no one component of the stress tensor correlates with the Raman peak shift generated by the deformed silicon. An analysis is developed to predict the Raman shift in deformed silicon that takes into account all the components of the stress or strain tensor; the results of the model are then used as inputs to the analysis for direct comparison with measured peak shifts as a function of distance from the TSV. Good agreement between the measured and predicted peak shifts is obtained for the case of the intact oxide stack. A discrepancy between the measured and predicted shifts was observed adjacent to the TSV with the oxide stack removed; further modeling suggests the discrepancy is explained by the formation of a small void at the TSV-silicon interface during etching. The combined measurement-modeling approach serves to both validate the model, in this case for TSV design, and to extend the measurement capability of confocal Raman microscopy to complex stress fields.

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“…Different techniques were used for via manufacturing with an aspect ration up to 30:1 [2] and various materials were used to create the conductive layers and to fill the via's [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

“…Comparing to other structures of this type previously made [3][4][5], we intended to deposit barrier and seed layers over via walls by PVD techniques.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of through-wafer interconnections by gold electroplating

Vasilache

Colpo

Giacomozzi

et al. 2011

CAS 2011 Proceedings (2011 International Semiconductor Conference)

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A new method for conductive via's using gold electroplating is presented. Tapered walls through wafer via (TWV) holes were made using a variable isotropy DRIE process, with a very good control over the obtained anglesangles of 11.3° and 21.8° were obtained with errors smaller than 10%. Barrier and seed layers were deposited in via's performed by PVD (Physical Vapor Deposition) techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via's.

show abstract

Development of cost-effective high-density through-wafer interconnects for 3D microsystems

Cited by 24 publications

References 4 publications

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via

Fabrication of through-wafer interconnections by gold electroplating

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