Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed.

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A novel scalable and stackable nonvolatile memory technology suitable for building fast and dense memory devices is discussed. The memory cell is built by layering a storage element and a selector. The storage element is a Phase Change Memory (PCM) cell [1] and the selector is an Ovonic Threshold Switch (OTS) [2]. The vertically integrated memory cell of one PCM and one OTS (PCMS) is embedded in a true cross point array. Arrays are stacked on top of CMOS circuits for decoding, sensing and logic functions. A RESET speed of 9 nsec and endurance of 10 6 cycles are achieved.One volt of dynamic range delineating SET vs. RESET is also demonstrated.

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