Recovery Effects in the Distributed Cycling of Flash Memories

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Charge trapping is also inserted in a phenomenological manner, in agreement with the observed square-root dependence on N C [221,222], resulting in the following expression for the average number of electrons being trapped at cycle N C :…”

“…Figure 21 shows instead the dependence on the bake conditions: note that the detrapping dynamics depend on the time t 0 elapsing between the last program and the first read operation (left-hand side), resulting in a shift of the detrapping curve along the log-time axis by a quantity exactly equal to t 0 . Also, ∆V T depends upon the bake temperature T B (right-hand side of Figure 21), demonstrating that detrapping is thermally activated: the ∆V T curves at different T B are shifted according to an Arrhenius law with activation energy E A ≈ 1.1 eV [221,222,228,229], a single detrapping curve can be obtained for an equivalent T B . This value of activation energy had been also observed in earlier retention experiments [51].…”

“…Moreover, as charge is trapped into the oxide during P/E cycling and detrapped in-between, a dependence on the cycling pattern arises, which complicates the development of comprehensive models. Such task began in [221,222] and developed into a full model accounting for the major experimental evidence in [223][224][225]. Figure 19 shows experimental data from a retention experiment at room temperature on a 16 nm NAND vehicle after 10 4 P/E cycles [226].…”

“…We start this Section with the description of a compact model [221,222,226] that captures the main features of the data and can be used for some first-order extrapolations, while moving to more refined descriptions of the underlying physics later on. To this aim, we assume a log-time dependence of the V T shift that, considering that the first read operation is performed at time t 0 after the end of the cycling phase, leads to…”

Reducing latency overhead caused by using LDPC codes in NAND flash memory

“…Electrons capture and emission events at charge trap sites near the interface developed over P/E cycling directly result in memory cell threshold voltage random fluctuation, which is referred to as random telegraph noise (RTN) [13,14]; http://asp.eurasipjournals.com/content/2012/1/203 2. Interface state trap recovery and electron detrapping [12,15] gradually reduce memory cell threshold voltage, leading to the data retention limitation. This is referred to as data retention noise.…”