Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling

Abstract

Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed.

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Charge trapping is also inserted in a phenomenological manner, in agreement with the observed square-root dependence on N C [221,222], resulting in the following expression for the average number of electrons being trapped at cycle N C :…”

“…Figure 21 shows instead the dependence on the bake conditions: note that the detrapping dynamics depend on the time t 0 elapsing between the last program and the first read operation (left-hand side), resulting in a shift of the detrapping curve along the log-time axis by a quantity exactly equal to t 0 . Also, ∆V T depends upon the bake temperature T B (right-hand side of Figure 21), demonstrating that detrapping is thermally activated: the ∆V T curves at different T B are shifted according to an Arrhenius law with activation energy E A ≈ 1.1 eV [221,222,228,229], a single detrapping curve can be obtained for an equivalent T B . This value of activation energy had been also observed in earlier retention experiments [51].…”

“…Moreover, as charge is trapped into the oxide during P/E cycling and detrapped in-between, a dependence on the cycling pattern arises, which complicates the development of comprehensive models. Such task began in [221,222] and developed into a full model accounting for the major experimental evidence in [223][224][225]. Figure 19 shows experimental data from a retention experiment at room temperature on a 16 nm NAND vehicle after 10 4 P/E cycles [226].…”

“…We start this Section with the description of a compact model [221,222,226] that captures the main features of the data and can be used for some first-order extrapolations, while moving to more refined descriptions of the underlying physics later on. To this aim, we assume a log-time dependence of the V T shift that, considering that the first read operation is performed at time t 0 after the end of the cycling phase, leads to…”

“…The experimental data presented so far and the physical understanding leading to Equation (11) led to the recognition that traditional testing procedures based on fast cycling and long retention times were magnifying the V T loss with respect to real usage conditions, when cycling takes place over the functional life of the device (see the effect of increasing t C in Figure 22, left). The concept of distributed cycling conditions was then proposed in [221] as a way to better emulate the real array behavior by performing either a uniform cycling over a longer time or several groups of fast cycles preceded by bake times, usually at high temperature to accelerate the charge loss. However, the previous model shows its limitations when dealing with highly non-uniform cycling patterns, calling for a more comprehensive interpretation of the trapping/detrapping physics, that was pursued in [223][224][225]227,233].…”