In this paper, a new accurate and low delay leakage current (h) model for complementary metal oxide semiconductor (CMOS) inverter is presented. During the overshooting period, the input-to-output coupling capacitance (eM) influence has been modeled regarding the short channel effect (SCE). Polynomial approximation is used to simplify and accelerate the model with very good accuracy. The time conditions for overshooting region (101') are also derived regarding leakage current and coupling capacitance influence. Performance evaluation of the proposed model is compared with simulated results of the BSIM4 level 54 model using HSPICE with very good agreement.
In this paper, a new accurate and efficient model for subthreshold leakage current is proposed for nanoscale metal oxide semiconductor field effect transistor (MOSFET). The influence of drain induced barrier lowering (DIBL) and gate induced drain lowering (GIDL) due to short channel effect (SCE) on subthreshold leakage is modeled and included in the characteristic equation. The linearization factor ( ) and subthreshold swing coefficient ( ) are modeled and included to make the proposed model faster than the recent published models. The evaluation of the proposed model shows very good agreement when compared with simulation results of BSIM4 Level 54 Model using HSPICE tool. Index Terms-Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Lowering (GIDL), linearization factor, ( ) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Short Channel Effect (SCE), Sub threshold leakage (I sub ).
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