Backscattering coefficient accurate model for nanoscale Si-MOSFET transistor

Rjoub, Abdoul; Al-Mistarihi, Mamoun F.; Al-Taradeh, Nedal R.

doi:10.1109/ftfc.2013.6577754

Cited by 1 publication

(1 citation statement)

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“…In 2011 a model based on trap assisted tunneling model has been proposed by [10]. As it is explained in [14], the flowing of electrons from the silicon to the oxide causes an image charge at the interface between the Si and SiO 2 on the oxide region, this cause also a remarkable reduction at the Oxide Electrostatic Potential (OEP) and causes an increasing in the gate current by the value of (ΔΦ ox ). According to the cancellation of negative and positive trap charge at the edge of the overlapping region near the gate side, the term of the flat band voltage will cancel each other, more details regarding this flat band voltage equation of the electric field for the overlapping region is given by [11,12] The total leakage overlapping leakage will be as in the equation (8) [11,12,15].…”

Section: Modeling Of Gate To Source and Drain Overlapping Leakagementioning

confidence: 99%

Accurate leakage current models for MOSFET nanoscale devices

Rjoub¹,

Mistarihi²,

Taradeh³

2020

IJECE

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This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

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