Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Al-Mistarihi, Mamoun F.; Rjoub, Abdoul; Al-Taradeh, Nedal R.

doi:10.1109/icm.2013.6735011

Cited by 11 publications

(7 citation statements)

References 5 publications

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“…ð Þ, surface potential ΦS T ð Þ , and flat-band voltage Vfb T ð Þ have been investigated for 4H-SiC and Si. 17,27 Vbi T It can be seen that as the temperature rises from 100 to 400 K, the concentration of electrons is lower in gate-stack DM NW FET (4H-SiC) due to larger band gap of 4H-SiC than Si which results in better mobility 17,22 and is preferred in various digital applications.…”

Section: Built-in Potential Vbi Tmentioning

confidence: 99%

“…As a result, the g m of a device is essential for designing and analyzing circuits for analog and RF applications. 27,30 Figure 9A,B depicts the g m variation of gate-stack DM NW FET (4H-SiC) and gate-stack DM NW FET (Si) w.r.t. V gs at different temperatures from 100 to 400 K at V ds = 1.0 V. g m rises as the temperature rises, leading to a change in carrier mobility due to change in the Fermi level.…”

Section: Built-in Potential Vbi Tmentioning

confidence: 99%

“…Built‐in potential

Vbi (T)

, surface potential

Φ S (T)

, and flat‐band voltage

Vfb (T)

have been investigated for 4H‐SiC and Si 17,27

Vbi (T) = \frac{italickT}{q} \ln (\frac{N_{a} N_{d}}{{ni}^{2} ((), Si / 4 normalH ‐ SiC)}),

{normalΦ}_{S} (T) = \frac{E_{g ((), Si / 4 normalH ‐ SiC)}}{2} + χ - q {normalΦ}_{f} (T),

V_{italicfb} (T) = ϕ_{m} - ϕ_{s} (T) .

…”

Section: Analytical Modelmentioning

confidence: 99%

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Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Neeraj

Sharma

Goel³

et al. 2022

Int J Numerical Modelling

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This article presents an analytical study and effect of temperature (T = 100, 200, 300, 400 K) on various parameters of gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW) FET (4H-SiC) and gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW FET) (Si). The parabolic approximation is used to solve the 2D Poisson's equation for surface potential, electric field, drain current (I ds ), transconductance (g m ), output conductance (g d ), and analog performance is evaluated. Electron concentration, electron velocity, drain induced barrier lowering, DIBL, and noise figure (NF) have also been investigated for a fair comparison and shows that 4H-SiC based gate-stack DM NW FET device is more insensitive to temperature changes than the silicon-based gate-stack DM NW FET. Furthermore, gatestack DM NW FET (4H-SiC) has better electrical performance with temperature variation than gate-stack DM NW FET (Si). The simulations have been carried out using the ATLAS 3D device simulator. Analytical results are in close agreement with the simulated results.

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Section: Built-in Potential Vbi Tmentioning

confidence: 99%

Section: Built-in Potential Vbi Tmentioning

confidence: 99%

See 1 more Smart Citation

Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Neeraj

Sharma

Goel³

et al. 2022

Int J Numerical Modelling

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“…We observe that the drain current increases in the I D -V DS characteristics with increasing of V GS compared to the 1 µm gate length device structure with a thicker oxide. However, despite a strengthening of a gate control by the oxide thickness reduction and aggressive doping in the channel, SCE occur in the scaled 0.25 µm gate length device, especially at higher V GS s. This is partially a result of increasing effect of the drain induced barrier lowering (DIBL) at very large applied drain voltages [26,27,28].…”

Section: Scaling Approach and Structure Optimisation Of The Scaled Domentioning

confidence: 99%

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Adenekan

Holland

Kálna

2019

Microelectronics Reliability

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The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 µm gate length SJ multigate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (R on,sp). We investigate scaling of the device architecture to improve the device performance by optimizing doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (R on,sp) of 7.68 mΩ.mm 2 and 2.24 mΩ. mm 2 (V GS = 10 V) and BV of 48 V and 26 V , respectively. The scaled 0.5 µm and 0.25 µm gate length SJ-MGFETs offer a transconductance (g m) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V , respectively, greatly improving the levels of integration in a CMOS architecture.

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“…Although extraordinary progress has been made, there are still lots of challenges if the performance of chips is expected to have further improvement involving mobility degeneration and further miniaturization [2,3]. However this seems an impossible task with traditional silicon technology due to physical limitation and severe short channel effect (SCE) [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] as the scaling-down continues.…”

Section: Introductionmentioning

confidence: 99%

Atomic-scale tomography of semiconductor nanowires

Ringer

Zheng

2015

Materials Science in Semiconductor Processing

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Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Cited by 11 publications

References 5 publications

Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Atomic-scale tomography of semiconductor nanowires

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Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Cited by 11 publications

References 5 publications

Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Temperature sensitive analytical analysis of gate‐stack dual metal nanowire field‐effect transistor (4H‐SiC)

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Atomic-scale tomography of semiconductor nanowires

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Product

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About

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications