Extreme energy constraints inherent in many exciting new wireless sensing applications (such as [1][2][3]) virtually dictate that such systems operate with extremely low duty cycles, harvesting and storing energy over long periods of time before waking up to perform brief measurement and communication tasks. However, such duty cycling only works if the sleep power of the system is less than the average power available from the power source, which may only be as much as a few nA. In this work, we present an RF transmitter designed to operate in an extremely low duty-cycle industrial monitoring system. The primary challenges are achieving high efficiency in the active mode while transmitting as high as +10dBm and simultaneously minimizing the leakage during the sleep mode. We address these in a +10dBm Bluetooth Low Energy (BLE) transmitter test-chip through 1) low voltage design (0.68V) for switching power and short-circuit power reduction, 2) extensive power gating of unused blocks and 3) a negative-VGS biasing technique for PA leakage reduction without affecting its on-performance.Typically, high-VT power switches are used to power gate low-VT active circuits [1]. But, the switch resistance, which is in the direct path of active current, degrades on-performance. Increasing switch size will in turn increase leakage. Negative gate-biasing of the gating switch has been shown to give significant leakage reduction [3]. However, in this work, we study the effect of negative-gate biasing of the low-VT active device itself, thereby eliminating a switch in the direct path of active current and simultaneously reducing leakage. This is especially useful for the PA in our work, which operates at +10dBm and is the largest active power consumer. Fig. 13.7.1 shows the measured drain current (ID,PA) and gate current (IG,PA) of the NMOS PA transistor as a function of the negative gate bias applied. The 65nm CMOS transistor, because of its thin gate oxide, has significant gate leakage. It is exponential with the gate bias. The drain current, which is the sum of sub-threshold current and gate leakage, decreases exponentially with increasing gate bias while the sub-threshold current is dominant, but increases as gate leakage becomes larger. The red curve (in solid) shows the achievable total PA leakage assuming the negative bias is supplied by an ideal −½ charge pump (ILEAK = ID,PA-½IG,PA). The minimum, 430pA, occurs at −200mV and represents a 30× reduction in leakage. Fig. 13.7.1 also shows a histogram of the minimum (ID,PA−½IG,PA) current for 25 measured chips. Simulations indicate that the minimum leakage points range from −150mV to −300mV, which implies that a −½ charge pump generating VNEG =−½VIN is sufficient. Low VDD ensures device reliability even with VNEG biasing (VDD-VNEG < 1.2V). Fig. 13.7.2 shows the complete TX system block diagram. The RF signal path has a 12MHz crystal oscillator feeding a divided 1MHz clock to an integer-N PLL. The PLL provides 2MHz-spaced BLE channels at 2.4GHz. The PLL output is then buffered ont...