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IEEE organization defined a standard for floatingpoint arithmetic, used by processing systems, in its directive 754 [1]. This directive encodes floatingpoint numbers using a maximum of 64 bits: 23 bit of fractional as single precision format and 52 bit of fractional as double precision format. The new multimedia terminals require low-power applications; the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modern System-OnChip. They might dissipate less power, using a reduced format representation. To verify this possibility, real systems simulate floating -point operations using different formats. In this conference paper, multimedia systems operate in different scenarios: wireless communication and image manipulation.