A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip

Ickes, Nathan; Sinangil, Yildiz; Pappalardo, F.; Guidetti, Elio; Chandrakasan, Anantha P.

doi:10.1109/esscirc.2011.6044889

Cited by 33 publications

(25 citation statements)

References 9 publications

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“…When idle, ULSNAP's timer coprocessor uses only 300 nW at nominal V DD , as compared to 400 µW for the coprocessor in [6]. We compared ULSNAP against various state-of-the-art microcontrollers [1][2][3][4][5] and present the results in Table II. Fig.…”

Section: Discussionmentioning

confidence: 99%

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ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes

Otero

Tse

Karmazin

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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Abstract-We present the architecture of and measured results for ULSNAP: a fully-implemented ultra-low power event-driven microcontroller targeted at the bursty workloads of the sensor network application space. ULSNAP is event-driven at both the microarchitectural and circuit levels in order to minimize static power, energy per operation, and wake up energy while maximizing performance. Our 90 nm test chip offers 93 MIPS at 1.2 V and 47 MIPS at 0.95 V, consuming 47 pJ and 29 pJ per operation respectively. Compared to state-of-the-art processors in its class, ULSNAP is on the Pareto-optimal front of the energyperformance space.

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Section: Discussionmentioning

confidence: 99%

“…Here, the sending process asserts the data 0 line to represent a false token (1), which the receiving process acknowledges (2). The channel then resets (3,4). As can be seen in Fig.…”

Section: Data-driven Qdi Designmentioning

confidence: 99%

ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes

Otero

Tse

Karmazin

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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show abstract

“…To enhance the SoCs power consumption, the core voltage supply is reduced, reaching in latest technology nodes a minimum voltage value of 0.6V [1]. The reduction is limited by the SRAM voltage scalability, which can remain at higher voltage using a secondary power supply source, however Von Neumann architectures first levels of memories (cache, register file) suffer from the induced higher interconnection delay [2].…”

Section: Introductionmentioning

confidence: 99%

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Abouzeid

Bienfait

Akyel

et al. 2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.

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“…It consumes only 15.6 pJ/Ops at 1.0 V. For the same supply voltage level (1.0 V), yet 130 nm process Kwong et al [15] report 47 pJ/cycle energy consumption for their 16-bit core where the number of clock cycle per instruction is higher than one. In another work, Ickes et al [16] introduce a 32-bit core implemented in 65 nm, and the energy consumption of the core [16] is estimated for 1.0 V between 19.7 pJ/Ops and 27.0 pJ/Ops. Compared to these state-of-theart processing cores, our optimized core consumes less energy per operations notably due to its simplified architecture as well as reduced instruction set, as explained in Section III-A.…”

Section: ) Energy Efficiency Of the Corementioning

confidence: 99%

Multi-core architecture design for ultra-low-power wearable health monitoring systems

Dogan¹,

Constantin²,

Ruggiero³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Personal health monitoring systems can offer a costeffective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultralow-power multi-core architecture featuring low-power cores, yet capable of executing biomedical applications, with multiple instruction and data memories, tightly coupled through flexible crossbar interconnects. This architecture also includes broadcasting mechanisms for the data and instruction memories to optimize system energy consumption by tailoring memory sharing to the target application. Moreover, the architecture enables power gating of the unused memory banks to lower leakage power. Our experimental results show that compared to the state-of-the-art, the proposed architecture achieves 39.5% power savings at high workload requirements (637 MOps/s), and 38.8% savings at low workload requirements (5 kOps/s), whereby leakage power consumption dominates.

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A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip

Cited by 33 publications

References 9 publications

ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes

ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

Multi-core architecture design for ultra-low-power wearable health monitoring systems

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