Multi-core architecture design for ultra-low-power wearable health monitoring systems

Abstract

Abstract-Personal health monitoring systems can offer a costeffective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultralow-power multi-core architecture featuring low-power cores, yet capable of executing biomedical applications, with multiple instruction and data memories, tightly coupled through flexible crossbar interconnects. This architecture also includes broadcasting mechanisms for the data and instruction memories to optimize system energy consumption by tailoring memory sharing to the target application. Moreover, the architecture enables power gating of the unused memory banks to lower leakage power. Our experimental results show that compared to the state-of-the-art, the proposed architecture achieves 39.5% power savings at high workload requirements (637 MOps/s), and 38.8% savings at low workload requirements (5 kOps/s), whereby leakage power consumption dominates.

Hardware/software approach for code synchronization in low-power multi-core sensor nodes

“…Hardware/Software elements Low-power multi-core WBSNs (e.g. [11] and [15]) typically presents a structure comprising a set of computing units interfaced to instruction and data memories (IM and DM) through interconnection networks, as depicted in Figure 2. Three properties, common in this family of systems, must be satisfied by the platform to apply the proposed synchronization method.…”

“…The authors of [11] and [15] have shown that, even in the field of embedded bio-signal analysis applications, where the computational demands are rather low, parallelism leads to high energy efficiency, especially when multiple cores can execute in lock-step, i.e. : they are at the same point of the program flow, so that a single instruction is fetched and delivered in parallel.…”

“…We considered a multi-core platform similar to the ones described in [11] and [15] employing parallel computing cores connected to multi-banked IM and DM through crossbars. In addition, the synchronizer unit proposed in Section III-A is integrated in the system and peripherals (such as ADCs) are interfaced using memory-mapped registers.…”

Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation

“…Also, the operating voltages for a processor are limited to the minimum-voltage required for the reliable operation of on-chip SRAM cache which fails when scaling down to ultra-low voltages because of its shrinking noise margins, Nevertheless, SRAM dominates the energy consumption among the components of a processor [11] and several alternative SRAM bit-cells have been proposed. These sub-threshold SRAM bit-cells have 8-transistors [12] or 10-transistors [13]- [15].…”

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

“…To maximize the overall efficiency of smart WBSNs, signal processing must therefore be supported within a tight power budget, while at the same time respecting real time constraints. In this regard, many efforts have been made in the last years, proposing solutions ranging from ad-hoc accelerators [10], [11] to ultra-low-power (ULP) multi-core architectures [8], [12].…”