2017
DOI: 10.1109/tc.2016.2610426
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A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

Abstract: Abstract-In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiograms, for periods of time extending from hours to days. The energy required for the on-node digital signal processing (DSP) is a crucial limiting factor in the conception of these devices. To address this design challenge, we introduce a domain-speci… Show more

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Cited by 13 publications
(10 citation statements)
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References 34 publications
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“…Many research works also design new techniques to increase the security and reliability of such systems like . Further, architecture‐level optimizations have been proposed in Wireless Body Sensor Nodes (WBSNs) that exploit emerging technologies, in order to reduce energy consumption and enhance performance …”
Section: Trends and Future Directionsmentioning
confidence: 99%
“…Many research works also design new techniques to increase the security and reliability of such systems like . Further, architecture‐level optimizations have been proposed in Wireless Body Sensor Nodes (WBSNs) that exploit emerging technologies, in order to reduce energy consumption and enhance performance …”
Section: Trends and Future Directionsmentioning
confidence: 99%
“…Our strategy shares some similarities with [13], [8], [27]. As opposed to [13], our methodology does not require a strict partitioning of the computations and of the data types between exact and approximate, an approach that places a high burden on application programmers.…”
Section: Inexact and Near-threshold Computingmentioning
confidence: 99%
“…As opposed to [13], our methodology does not require a strict partitioning of the computations and of the data types between exact and approximate, an approach that places a high burden on application programmers. With respect to [8], we do not restrict the fault-prone memory area to a portion of the data memory; on the contrary, we consider (and manage) faults in the entire memory system, including the whole data memory (comprising dynamic structures such as the stacks) as well as the instruction memory. In [27] and [17], related error recovery strategies are investigated.…”
Section: Inexact and Near-threshold Computingmentioning
confidence: 99%
“…First, we analyze their application-level effect on two real-world bio-DSP benchmarks. Then, we introduce [7] CGRA acceleration Inexact computing [8] SIMD, multicore [9]- [11] [12]…”
Section: Introductionmentioning
confidence: 99%