Abstract-Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by chronic ailments. Nowadays, WBSNs often embed complex digital processing routines, which must be performed within an extremely tight energy budget. Addressing this challenge, in this paper we introduce a novel computing architecture devoted to the ultra-low power analysis of biosignals. Its heterogeneous structure comprises multiple processors interfaced with a shared acceleration resource, implemented as a Coarse-Grained Reconfigurable Array (CGRA). The CGRA mesh effectively supports the execution of the intensive loops that characterize bio-signal analysis applications, while requiring a low reconfiguration overhead. Moreover, both the processors and the reconfigurable fabric feature Single-Instruction / MultipleData (SIMD) execution modes, which increase efficiency when multiple data streams are concurrently processed. The run-time behavior on the system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors for SIMD execution and regulates access to the reconfigurable accelerator. By jointly leveraging run-time reconfiguration and SIMD execution, the illustrated heterogeneous system achieves, when executing complex bio-signal analysis applications, speedups of up to 11.3x on the considered kernels and up to 37.2% overall energy savings, with respect to an ultra-low power multicore platform which does not feature CGRA acceleration.
Abstract-Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, thanks to their flexibility and high computational density, they can efficiently support the computational hot-spots characterizing bio-DSP applications. The InterleavedDatapaths (i-DPs) CGRA presented in this paper further leverages the benefits of this architectural paradigm, focusing on ultralow energy operation. Its defining feature is the complex design of its computing cells, which, by embedding multiple i-DPs, allow a high ratio between computing and control logic, effectively speeding up computations, and resulting in a marginal impact on the required IC area. Interleaved datapaths increase the energy efficiency of up to 33 %, with respect to a single-DP alternative, when executing common kernels in the multi-lead ECG signal processing field.
Abstract-This paper introduces a novel computing architecture devoted to the ultra-low power analysis of multiple biosignals. Its structure comprises several processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable Array (CGRA). The CGRA supports the efficient execution of the computationally intensive kernels present in this application domain, while requiring a low reconfiguration overhead. The run-time behavior of the resulting heterogeneous system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors and regulates access to the reconfigurable accelerator. The architecture achieves speed-ups of up to 11x on different bio-signal processing kernels and system-level energy savings of up to 18.6%, with respect to a multi-core platform, which does not feature CGRA acceleration.
e energy e ciency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is o en bounded by reliability concerns, especially since static and dynamic non-idealities are exacerbated in the near-threshold region, imposing costly guard-bands to guarantee correctness under worst-case conditions. A striking alternative, explored in this paper, waives the requirement for unconditional correctness, undergoing more relaxed constraints. First, a er a run-time failure, processing correctly resumes at a later point in time. Second, failures induce a limited ality-of-Service (QoS) degradation. We focus our investigation on the practical scenario of embedded bio-signal analysis, a domain in which energy e ciency is key, while applications are inherently error-tolerant to a certain degree. Targeting a domain-speci c multi-core platform, we present a study of the impact of inexactness on application-visible errors. en, we introduce a novel methodology to manage them, which requires minimal hardware resources and a negligible energy overhead. Experimental evidence show that, by tolerating 900 errors/hour, the resulting inexact platform can achieve an e ciency increase of up to 24%, with a QoS degradation of less than 3%. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permi ed. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. INTRODUCTIONe emergence of embedded devices, able to continuously acquire and wirelessly transmit the sensed data, is fostering a revolution across the IT landscape [3], opening novel and exciting opportunities in many elds, ranging from environmental protection [30] to domotics [16].Among them, healthcare applications are of particular interest, especially the ones related to monitoring chronic cardiovascular disorders [1]. In this scenario, sensor appliances (named Wireless Body Sensor Nodes, WBSNs) enable the long-term acquisition of bio-signals, outside of a hospital environment and with minimal medical supervision [18].E ciency is key for WBSNs, as the saved energy translates both in smaller form factors (by requiring smaller ba eries) and longer autonomies. Herein, we focus our investigation on the energy optimization of the Digital Signal Processing (DSP) applications executing on WBSNs. Such routines analyze acquisitions, deriving compact feature sets, which are then transmi ed on the wireless link [7]. ey must be supported within a tight energy envelope, because...
Energy consumption is a significant obstacle to integrate deep learning into edge devices. Two common techniques to curve it are quantization, which reduces the size of the memories (static energy) and the number of accesses (dynamic energy), and voltage scaling. However, static random access memories (SRAMs) are prone to failures when operating at sub-nominal voltages, hence potentially introducing errors in computations. In this paper we first analyze the resilience of artificial intelligence (AI) based methods for edge devicesin particular convolutional neural networks (CNNs)-to SRAM errors when operating at reduced voltages. Then, we compare the relative energy savings introduced by quantization and voltage scaling, both separately and together. Our experiments with an industrial use case confirm that CNNs are quite resilient to bit errors in the model, particularly for fixed-point implementations (5.7 % accuracy loss with an error rate of 0.0065 errors per bit). Quantization alone can lead to savings of up to 61.3 % in the dynamic energy consumption of the memory subsystem, with an additional reduction of up to 11.0 % introduced by voltage scaling; all at the price of a 13.6 % loss in accuracy.
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