Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

Abstract

Energy consumption is a significant obstacle to integrate deep learning into edge devices. Two common techniques to curve it are quantization, which reduces the size of the memories (static energy) and the number of accesses (dynamic energy), and voltage scaling. However, static random access memories (SRAMs) are prone to failures when operating at sub-nominal voltages, hence potentially introducing errors in computations. In this paper we first analyze the resilience of artificial intelligence (AI) based methods for edge devicesin particular convolutional neural networks (CNNs)-to SRAM errors when operating at reduced voltages. Then, we compare the relative energy savings introduced by quantization and voltage scaling, both separately and together. Our experiments with an industrial use case confirm that CNNs are quite resilient to bit errors in the model, particularly for fixed-point implementations (5.7 % accuracy loss with an error rate of 0.0065 errors per bit). Quantization alone can lead to savings of up to 61.3 % in the dynamic energy consumption of the memory subsystem, with an additional reduction of up to 11.0 % introduced by voltage scaling; all at the price of a 13.6 % loss in accuracy.

On the Resilience of Deep Learning for Reduced-voltage FPGAs

“…Also, unlike the fully hardware-based approach, our study is more facilitated and can be easily expanded for many different applications. In other words, our approach has the advantage of both full software [45], and fully real hardware [46] resilience study approaches, similar to recent works [43], [47], [48].…”

“…The verification of the simulation-based works on the real fabric can be a crucial concern; also, the real hardware works are mostly performed on the customized ASICs, which of course, reproducing those results on the COTS systems is a crucial question. On the other hand, there are not thorough efforts on the resilience of the DNN training phase; recent works in part cover the study in this area [24], [25], [40]- [42]. For instance, [41], [42] have analyzed only the fully-connected model of DNNs, [24] carried out the analysis on a customized ASIC model of the DNN, and finally, [25] performed a simulationbased study.…”

Using Algorithmic Transformations and Sensitivity Analysis to Unleash Approximations in CNNs at the Edge

“…While, in principle, quantization may be performed considering arbitrary bitwidths [ 14 ], such fine-grained flexibility usually incurs vast overheads. Additional logic can instead be minimized when the adopted quantization levels are SIMD standard bitwidths (e.g., quantization on 16, 8, or 4 bits, as in [ 12 , 15 ]), since, in this case, word-level parallelism can be effectively employed.…”

A Hardware/Software Co-Design Vision for Deep Learning at the Edge

“…Although aggressive voltage reduction is possible as digital logic is error-resilient down to the technology voltage threshold, memories (e.g., SRAM cells) usually start failing at higher voltages, hence posing a limit to voltage scaling. The impact of memory errors due to voltagescaling on CNN accuracy has been studied in [11] and [2], showing that ensembling improves the robustness of CNNs, allowing SRAM memories to operate at sub-nominal voltages while coping with the ensuing errors. These works show energy savings in memories of up to 90% due to voltage scaling while limiting CNN output quality degradation caused by memory errors to just 1%.…”