This work presents an open-source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojan. A repository of RT-level benchmarks with different types of Hardware Trojan is available at the Trust-hub (https://www.trust-hub.org/resources/ benchmarks). Unfortunately, this benchmark suite misses completely the behavioral abstraction level. This work aims at bridging this gap by providing the first behavioral synthesis benchmark suite in a common language supported by all major HLS vendors (SystemC) which cover most of the hardware Trojan types. The designs have been created in such a way that the hardware Trojan cannot be found using standard software profiling techniques (i.e., 100% code coverage in most of the cases). This work also presents the obfuscated version of the benchmarks which makes it even hard to detect the hardware Trojans using the traditional verification approaches.
This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojanfree (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the case of BIPs, this is extremely hard, as it is a market still in its infancy. Moreover, it is very difficult to find HW Trojan at the system level as the trigger condition might be visible only when the system is fully functional. Thus, this work proposes the inclusion of a small HW Trojan detection circuit called trust filters to detect HW Trojan at runtime. With the help of cycle-accurate simulation model, it is possible to fine tune these filters so that the overall system has no performance degradation. This can be achieved by exploiting the slack time between the time that a slave returns the data to the master and the time that the master sends new data to the slave. The advantages of using C-based design are multi-fold: (i) It allows the generation of fast cycle-accurate models to measure the exact slack of each BIP mapped as a loosely coupled Hardware Accelerator (HWAcc) slave and (ii) its ability to build the complete SoC using synthesizable Application Programming Interfaces (APIs) and hence allowing the fine tuning of these trust filters. Experimental results show that our proposed architecture is very efficient leading to no performance penalties in many cases and has very small area overhead.Keywords High-level synthesis · Hardware trojan · Behavioral MPSoC · Third party behavioral IP (3PBIP)
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA softprocessor. The compiler automatically generates custom instructions in the security critical segments of the program, and the instructions execute on the RISC-V custom co-processor to produce diversified timing characteristics on each execution instance. CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs. Experimental results show that our solution can achieve 80% and 86% timing side-channel capacity reduction for two benchmarks with an acceptable performance overhead compared to existing solutions. In addition, the proposed method incurs only a negligible hardware area overhead of 1% slices of the entire RISC-V system.
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