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This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adpative Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (Cy-berWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.

A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for high-level synthesis based on a divide and conquer method called Divide and Conquer Exploration Algorithm (DC-ExpA) is presented. DC-ExpA parses an untimed behavioral description given in C or SystemC and clusters interdependent operations which are in turn explored independently by inserting synthesis directives automatically in the source code. The method then continues by combining the exploration results to obtain only Paretooptimal designs. This method accelerates the design space exploration considerably and is compared against two previous methods: an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) that shows good optimality at high runtimes, and a pattern matching method called Clustering Design Space Exploration Acceleration (CDS-ExpA) that is fast but suboptimal. Our proposed method is orthogonal to previous exploration methods that focus on the exploration of resource constraints, allocation, binding, and/or scheduling. Our proposed method on contrary sets local synthesis directives that decide upon the overall architectural structure of the design (e.g., mapping certain arrays to memories or registers). Results show that DC-ExpA explores the design space on average 61% faster than ASA-ExpA, obtaining comparable results indicated by several quality indicators, for example, distance to reference Pareto-front, hypervolume, and Pareto dominance. Compared to CDS-ExpA it is 69% slower, but obtains much betters results compared to the same quality indicators. ACM Reference Format:Carrion Schafer, B. and Wakabayashi, K. 2012. Divide and conquer high-level synthesis design space exploration.

High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.Index Terms-Benchmark testing, design automation, high level synthesis.

This paper presents a modified technique of simulated annealing, based on machine learning for effective multi-objective design space exploration in High Level Synthesis (HLS). In this work, we present a more efficient simulated annealing called Fast Simulated Annealer (FSA) which is based on a decision tree machine learning algorithm. Our proposed exploration method makes use of a standard simulated annealer to generate a training set, and uses this set to implement a decision tree. Based on the outcome of the decision tree, the algorithm fixes the synthesis directives (pragmas) which contribute to minimizing/maximizing one of the cost function objectives and continues the annealing procedure using the decision tree. Experimental results show that the average execution time of our proposed tree based simulated annealing algorithm is on average 36% faster than the standard annealer and can be up to 48% faster, while leading to similar results.