CIDPro: Custom Instructions for Dynamic Program Diversification

Abstract

Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA softprocessor. The compiler automatically generates custom instructions in the security critical segments of the program, and the instructions execute on the RISC-V custom co-processor to produce diversified timing characteristics on each execution instance. CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs. Experimental results show that our solution can achieve 80% and 86% timing side-channel capacity reduction for two benchmarks with an acceptable performance overhead compared to existing solutions. In addition, the proposed method incurs only a negligible hardware area overhead of 1% slices of the entire RISC-V system.

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage

“…Side Channel Software based Hardware based invasive non-invasive [3], [4] power dummy loops [8] power shuffling, noise instr. [9], [10] power enhancing algorithms [11] time [12], [13] power This work power countermeasure is dependent on the implementation of the algorithm software. In addition, a secure processor which can protect against side-channel attacks using masking and hiding techniques was proposed in [13].…”

“…These approaches result in a significant increase in hardware usage. Interestingly, a hardware-based non-invasive approach was presented in [11]. This countermeasure avoids substantial changes to processor architecture and effectively reduces timing side-channel leakage.…”