In order to develop high density NAND Flash device, the increased number of cell strings for 1 pag e buffer f orces to _ form a long bit-line with low sheet resistance, as well as low SitD parasitic capacitance between bit-lines. In this paper, we D secured a copper damascene process to form 38nm bit-lines(1) Photo Resist patterning with 76nm pitch using SADP (Self-Aligned Double Patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND Flash device with 38nm node technology.

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As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ~0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO 2 used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO 2 deposition on the formation of micro-bridge using in-house tool, PIE simulator.