Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Hwang, B.J.; Han, Jin-Tae; Kim, Myeong-Cheol; Jung, Sunggon; Lim, Namsu; Jin, Sowi; Yim, Yong-Sik; Kwak, Dong-Hwa; Park, Jaekwan; Choi, Jaehyuk; Kim, Kinam

doi:10.1109/essderc.2009.5331401

Cited by 4 publications

(2 citation statements)

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“…This implies that the trimmed pattern density is indeed smaller than that of the pattern prepared by the conventional lithography. The alternative solution for pattern density improvement is to integrate the Trimming lithography with the double patterning technique [8]. The 2 µm designed pattern is applied next to observe the effects of the trimming distance to the pattern quality.…”

Section: Effects Of Trimming Distance To the Pattern Qualitymentioning

confidence: 99%

Trimming Lithography: An Alternative Technology for Sub-Resolution and Sub-Wavelength Patterning

et al. 2012

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Lithography is one of the key technologies for scaling down a size of integrated circuits thus increasing the performance of an electronic device. Currently, there are many lithographic techniques that are potentially capable to produce a nanometer feature size but the continuing development for a commercial use is still limited by extremely high investment especially on exposure equipment and mask. This paper introduces an alternative patterning technique called Trimming lithography as one of the strong candidates for future lithography, for producing sub-resolution and subexposure wavelength features. The pattern size can be downscaled by carefully adjusting the trim distance that is much higher than an original design linewidth. It is shown that the photoresist (PR) feature size can be scaled down with the acceptable profile to approximately 0.18 m from the original 0.8 m mask pattern with the 0.5 m resolution of the exposure tool. However, the pattern density of the line/space pattern becomes lower than that of the typical lithography. Different pattern qualities between dense and isolated patterns are probably explained by a diffraction occurring during a transmission of light through the mask slit.

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Section: Effects Of Trimming Distance To the Pattern Qualitymentioning

confidence: 99%

Trimming Lithography: An Alternative Technology for Sub-Resolution and Sub-Wavelength Patterning

et al. 2012

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“…Some of these worth mentioning that are already incorporated into devices or that are being actively studied for potential deployment are advanced multi-layered gate stacks such as SONOS [58], TANOS [101], high-k dielectrics [193], nanocrystals [126], double patterning [59], MLC programming (3 bits per cell is already demonstrated) [141] and a 3-dimensional channel structure for future Tbit storage [77]. Some of these worth mentioning that are already incorporated into devices or that are being actively studied for potential deployment are advanced multi-layered gate stacks such as SONOS [58], TANOS [101], high-k dielectrics [193], nanocrystals [126], double patterning [59], MLC programming (3 bits per cell is already demonstrated) [141] and a 3-dimensional channel structure for future Tbit storage [77].…”

Section: Overview Of Flash Memory and Other Leading Contendersmentioning

confidence: 99%