We evaluate several types of wafers and investigate the effect of wafer edge geometry on focus, dynamics and defectivity performance in ArF immersion lithography. Wafer edge geometry includes both edge shape (e.g. short, long, full round etc.) and edge roll-off (ERO) here. We found that focus accuracy at wafer edge depends on ERO, especially on ZDD (Z double derivative) and if we use the specified wafer which has low ZDD value, it keeps same good focus accuracy at the edge area as the one at the wafer center area. Dynamics (stage synchronization accuracy) was independent of wafer diameter, thickness and edge geometry. We also found that defectivity was strongly dependent on the edge shape. More bridging defects were found on the short edge wafer than the long edge wafer. This is related with wafer edge conditions after coating and during exposure.
Electron beam (EB) direct writing systems have often been used for fabricating sub-half-micron advanced devices because EB direct writing is the most practical method for making the required patterns. Recently, the cell projection (CP) method has become indispensable for increasing the writing throughput in the EB direct writing system. However, it is considered that resist heating may be seriously aggravated below the quarter-micron level when the CP method is used, because the total deposited energy, which is irradiated by one CP EB shot, is almost the same as that irradiated by one variably shaped (VS) EB maximum size shot. Resist heating in the case of the CP method is calculated by a finite element method using the ANSYS (Ver. 5.0A: ANSYS, Inc.) program. In particular, thermal diffusion calculation is mainly carried out under the conditions of 50 kV acceleration voltage and 10 A/cm2 current density for practical application to advanced device fabrication. The calculated results suggest that resist heating in the CP method is mainly caused by the horizontal thermal flux between plural EB shots within the area of one CP shot, by the same mechanism as proximity resist heating under the VS method. Therefore, CP EB writing causes horizontal-mode resist heating. In particular, when a low current density is used, this resist heating mode arises significantly. However, CP writing with high acceleration voltage causes a reduction in the rise of the resist temperature, which causes resist heating. When the EB irradiation time is longer than 1.0 µ s under practical EB writing conditions, the resist temperature increases proportionally to the decrease of writing pattern size in the case of the CP writing with a maximum shot size of 5.0×5.0 µ m. It is also shown that the larger the beam blur of an incident beam, the more serious is the resist heating. When a highly sensitive resist (10 µ C/cm2) is used under these practical conditions, however, resist heating in the CP method is prevented without writing throughput degradation regardless of the CP maximum shot size, because the resist temperature does not rise above the thermal denaturation temperature of standard EB resists. Accordingly, the maximum CP shot size, which affects the writing throughput, is determined by the proximity effect and the Coulomb interaction for fine pattern fabrication.
This paper describes 0.15 µ m electron beam (EB) direct writing techniques for Gbit dynamic random access memory (DRAM) fabrication. In order to use EB direct writing for reliable fine pattern fabrication on the 0.15 µ m level, an EB direct writing system technique, a resist process technique, a cell projection (CP) mask preparation technique, which is indispensable for improving the writing throughput, and a data preparation technique with proximity effect correction must be improved respectively and combined successfully. The proximity effect correction for all fine patterns in a full-scale DRAM chip is especially important for achieving a CD accuracy of less than 0.02 µ m, which is required for device fabrication and margin. For obtaining the reliable shot stitching accuracy between CP and variably shaped (VS) EB writings, we adopted the cross-correlation method, which was used to decide the size and center position of the CP shot. A single-layer resist system without an over-coated conducting layer was used for reliable device fabrication. In addition, for improving the CD accuracy for all 0.15 µ m designed patterns in a full-scale chip, we developed a data partition process suitable for CP mask pattern data and an improved 1-dimenshinal(1-D) calculation method for proximity effect correction. Utilizing these techniques, the full-scale 4Gbit DRAM, which was designed with 0.15 µ m minimum feature size, was fabricated successfully with 0.05 µ m (| mean|+3σ) overlay accuracy, 0.02 µ m (| mean+3σ) stitching accuracy, and less than 0.02 µ m (3σ) CD accuracy, all of which were sufficient for the required device fabrication.
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