A W -W e have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high s eed test requires only a low speed interface and standar B low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip hi h speed clock with frequency adjustable from 4 to 16 8Hz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have inteerated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported highspeed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test vanous RSFQ circuits.
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency.
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