Abstract-We believe that the best chance to observe macroscopic quantum coherence (MQC) in an rf-SQUID qubit i s to use on-chip RSFQ digital circuits for preparing, evolving and reading out the qubit's quantum state. This approach allows experiments to be conducted on a very short time scale (sub-nanosecond) without the use of large bandwidth control lines that would couple environmental degrees of freedom to the qubit, thus contributing to its decoherence. In this paper we present our design of an RSFQ digital control circuit for demonstrating MQC in an rf-SQUID. We assess some of the key practical issues in the circuit design including the achievement of the necessary flux bias stability. We present an "active" isolation structure to be used to increase coherence times. The structure decouples the SQUID from external degrees of freedom, and then couples it to the output measurement circuitry when required, all under the active control of RSFQ circuits.Index Terms-superconducting qubit, macroscopic quantum coherence, RSFQ control.
Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm 2 ), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of selfheating and models for the generation and propagation of sub-ps single-flux-quantum pulses.
A W -W e have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high s eed test requires only a low speed interface and standar B low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip hi h speed clock with frequency adjustable from 4 to 16 8Hz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have inteerated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported highspeed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test vanous RSFQ circuits.
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